Verilog vhdl punët

...verification. • Build the directed and random verification tests, debug test failures to determine the root cause, work with RTL and firmware engineers to resolve design defects and correct any test issues. • Work on functional & code coverage verification. • Provide technical support to other teams PREFERRED EXPERIENCE: • Experience with C/C++ • Experience with Verilog, System Verilog, and modern verification libraries like UVM • 6years of ASIC design verification experience • Experience / Background with DDR or Memory Controller. PHY Verification is a plus • Experience with scripting languages like Python, Perl and TCL is a plus. • Collaborate with architects, hardware...

...verification. • Build the directed and random verification tests, debug test failures to determine the root cause, work with RTL and firmware engineers to resolve design defects and correct any test issues. • Work on functional & code coverage verification. • Provide technical support to other teams PREFERRED EXPERIENCE: • Experience with C/C++ • Experience with Verilog, System Verilog, and modern verification libraries like UVM • 6years of ASIC design verification experience • Experience / Background with DDR or Memory Controller. PHY Verification is a plus • Experience with scripting languages like Python, Perl and TCL is a plus. • Collaborate with architects, hardware...

I need a fully-synthesizable VHDL implementation of a single-system GPS L1 C/A receiver that carries the signal all the way from raw I/Q samples through acquisition, tracking, navigation decoding, and a basic PVT solver that delivers standard-accuracy position, velocity, and time. The acquisition stage must use a true parallel-search architecture; serial search or matched-filter alternatives are out of scope for this project. The code has to be cleanly structured, well-commented, and accompanied by self-checking test benches that exercise every major block—acquisition engine, tracking loops (DLL, PLL/FLL), data demodulator, ephemeris parser, and the fixed-point PVT routine. Simulation should run in Vivado or an equally common VHDL simulator, with clear instructions on ...

Assalam o alaikum, I am looking for electrical engineers having expertise in following areas:  Embedded C Programming.  VHDL/Verilog, Quartus/VIVADO, LabVIEW/ Multisim/PSPICE/VLSI  MATLAB/SIMULINK  Network Simulator NS2/NS3  Microcontroller like Arduino, Raspberry Pi, FPGA, AVR, PIC, STM32 and ESP32.  IDEs like Keil MDK V5, ATmel studio and MPLab XC8.  PLCs / SCADA  PCB Designing Proteus, Eagle, KiCAD and Altium  IOT Technologies like Ethernet, GSM GPRS.  HTTP Restful APIs connection for IOT Communications. Actually I have multiple projects in different domains of electrical engineering and I already have a team of engineers working on them but due to workload I am looking for few more engineers to be a part of my team and work with us on regular basis.

I'm seeking an experienced FPGA developer to help debug logical errors in existing VHDL code for a Lattice Semiconductor MachX03 development board. Key Requirements: - Expertise in VHDL - Experience with Lattice Semiconductor FPGAs - Strong debugging skills, especially with logical errors Ideal Skills and Experience: - Proven track record in FPGA development and debugging - Familiarity with MachX03 specific features and tools - Ability to provide clear, concise solutions and documentation Looking forward to your expertise!

I'm in need of a professional with VLSI (Verilog HDL,System verilog and matlab) expertise to help me with an IEEE paper, its design and implementation. The specific areas to be covered include simulation and testing, performance optimization, and power consumption management. FPGA Image Processing 1. I need to work on a project and implement a novel idea related to FPGA-based image processing. 2. I have the following tools available: o Xilinx Vivado 2018.2 and Xilinx Vivado 2025.1 o MATLAB 2024a and Simulink o Python simulation tools. Task: • Read an image (in BMP, .hex, or .coe format). or camera • Refer to a recent IEEE research journal (preferably from the year 2025) for guidance or inspiration. (Focus on novelty, performance (area,speed, resource usage,et...

...production contract covering up to 8,000 diagrams, with further scale potential. Project Overview The objective is to collect and deliver technical diagram images representing electrical and digital design concepts, paired with either: Verilog HDL code, or Clear, structured technical explanations in English These assets will be used in advanced AI/ML and engineering research applications. Dataset Requirements Each diagram must conform to one of the following variants: Variant 1 Original technical diagram image Corresponding Verilog Hardware Description Language (HDL) code Variant 2 Original technical diagram image Detailed English technical description explaining the circuit’s function and behavior All diagrams must be original and bui...

I have already begun converting the VHDL Language Reference Manual—about 700 pages—from its original PDF to LaTeX, but only scattered portions are finished. Roughly the first nine sections of the thirty-four total have a draft translation; the rest is still untouched or only partially copied over. All existing .tex sources, my compile script, and the official style guidelines (custom class file, macro set, and layout notes) will be in the hand-off package so you can follow the exact formatting rules that match the published standard. Figures, tables, and cross-references must render cleanly under pdflatex without manual post-processing. What I need from you is the full, consistent LaTeX source that: • covers every remaining section and appendix, completing the 70...

...tied to tape-out milestones. Your compensation is therefore predictable and performance-linked rather than speculative. Roles we still need to fill (4+ yrs exp each) System architects, embedded and systems programmers, verification engineers, physical design specialists, DevOps for CI/CD of RTL builds, HR lead for technical hiring, tech managers and team leads. Solid command of SystemVerilog/VHDL, C/C++, Linux kernel or Yocto, scripting, and modern EDA toolchains (Synopsys, Cadence, Siemens) is expected. What to include in your application Show me clear evidence of relevant experience—projects you’ve taken from spec to silicon or to FPGA prototypes, particularly for computing devices. Mention any industry connections (fabs, EDA vendors, IP houses) you can bring;...

...tied to tape-out milestones. Your compensation is therefore predictable and performance-linked rather than speculative. Roles we still need to fill (4+ yrs exp each) System architects, embedded and systems programmers, verification engineers, physical design specialists, DevOps for CI/CD of RTL builds, HR lead for technical hiring, tech managers and team leads. Solid command of SystemVerilog/VHDL, C/C++, Linux kernel or Yocto, scripting, and modern EDA toolchains (Synopsys, Cadence, Siemens) is expected. What to include in your application Show me clear evidence of relevant experience—projects you’ve taken from spec to silicon or to FPGA prototypes, particularly for computing devices. Mention any industry connections (fabs, EDA vendors, IP houses) you can bring;...

...multi-disciplinary expert or a small team to assist in a high-fidelity hardware research project focused on PCIe device emulation and DMA-based memory forensics. The goal is to develop a custom FPGA-based solution that can perfectly mimic a legitimate consumer PCIe device (e.g., Network or Storage Controller) to pass low-level system integrity checks. Key Responsibilities: Emulation (FPGA/Verilog): Develop custom firmware for an Artix-7/35T/75T FPGA board to emulate a real-world donor device's configuration space and TLP behavior. Development (C/C++): Create a high-performance Windows/Linux driver for direct memory access via the PCIe bus, ensuring stability and low latency. Analysis: Design a system to read and analyze specific application memory segments in real-time

I need a digital-only control circuit taken from concept through a production-ready schematic. The task sits firmly in the circuit-design branch of electrical engineering: no analog front-end...straight to PCB layout later. • Provide accompanying design files: schematics, netlist, component libraries, and a concise design-rules document. • Run basic simulations or logic-timing checks to verify that the circuit meets the specified control timings before hand-off. Everything should stay purely digital; no mixed-signal blocks are expected at this stage. If you are comfortable with Verilog/VHDL for behavioural validation, that is a plus but not mandatory—the key deliverable is a schematic ready for layout and prototyping. Let me know your favourite toolchain ...

I need a digital-only control circuit taken from concept through a production-ready schematic. The task sits firmly in the circuit-design branch of electrical engineering: no analog front-end...straight to PCB layout later. • Provide accompanying design files: schematics, netlist, component libraries, and a concise design-rules document. • Run basic simulations or logic-timing checks to verify that the circuit meets the specified control timings before hand-off. Everything should stay purely digital; no mixed-signal blocks are expected at this stage. If you are comfortable with Verilog/VHDL for behavioural validation, that is a plus but not mandatory—the key deliverable is a schematic ready for layout and prototyping. Let me know your favourite toolchain ...

I’m looking for an experienced Digital VLSI / ASIC engineer to complete a small end-to-end RTL-to-power analysis project using Cadence tools. The project follows a standard ASIC front-end flow: RTL design → synthesis → gate-level simulation → power estimation. All project structure, templates, and documentation are provided.

I’m looking for an experienced Digital VLSI / ASIC engineer to complete a small end-to-end RTL-to-power analysis project using Cadence tools. The project follows a standard ASIC front-end flow: RTL design → synthesis → gate-level simulation → power estimation. All project structure, templates, and documentation are provided.

I’m looking for an experienced Digital VLSI / ASIC engineer to complete a small end-to-end RTL-to-power analysis project using Cadence tools. The project follows a standard ASIC front-end flow: RTL design → synthesis → gate-level simulation → power estimation. All project structure, templates, and documentation are provided.

will share info in chat. only professional worker

I need a complete RTL design in Vivado that produces an up-chirp based on a sinusoidal input and sweeps from 50 MHz up to 55 MHz. Once generated, this signal must feed directly into an 8192-point FFT, so I can observe the dominant frequency bins in hardware. The core tasks are: • Write synthesizable VHDL / Verilog for the chirp oscillator, parameterised for the 50–55 MHz sweep. • Instantiate and configure the Xilinx FFT IP for 8192 points, wire it to the chirp stream, and handle any required data-format conversions or hand-shaking. • Provide timing-compatible top level, constraints, and a self-checking test-bench that sweeps the chirp, captures the FFT output, flags the peak bins and dominant frequencies. Acceptance is straightforward: when I run t...

...HDMI transmitter. I need a complete Vivado project that captures 1080p video from both ADV7611 receivers, performs basic in-FPGA signal processing (frame buffering, colorspace conversion or simple image filter—whichever is cleanest to showcase the path), and then drives the SiI9134 so the processed stream displays correctly on an external monitor. The project must be written in synthesizable Verilog or VHDL, use the latest Vivado tool-flow, and include: • Top-level RTL connecting the ADV7611 I²C, video, and clock lines to the SiI9134 interface on the XC7A200T • A timing-clean 148.5 MHz pixel clock domain plus any required gearboxes or FIFOs for 1080p@60 Hz • Minimal but working video-processing block(s) showing real-time manipulation (e.g., ...

I'm seeking an experienced developer to design an application-specific vector processor, primarily for scientific computing. This processor will be targeted for embedded systems and should be developed using Verilog or VHDL. Key Requirements: - Design and implement a vector processor architecture. - Optimize the processor for scientific computing tasks. - Ensure compatibility and efficiency on embedded systems. - Develop in Verilog or VHDL. Ideal Skills and Experience: - Strong background in digital design and hardware description languages (Verilog/VHDL). - Experience with embedded systems and scientific computing applications. - Ability to optimize hardware for specific workloads. Please provide a portfolio showcasing similar projects and...

I am looking for an experienced FPGA developer to write functional Verilog code for interfacing a 1-wire secure EEPROM with a Zynq Zed Board. The EEPROM includes SHA-1 authentication. The deliverables should include: - Fully functional Verilog code for the interface. - Proper handling of SHA-1 authentication. - Compatibility with the Zynq Zed Board.

I have already drafted a Smart Parking Gate Controller and will share the exact list of inputs, outputs, and the eight required operations as soon as we start. What I need now is the complete digital logic implementation: • Build the full truth table from my specifications. • Derive simplified Boolean expressions (K...outputs, and the eight required operations as soon as we start. What I need now is the complete digital logic implementation: • Build the full truth table from my specifications. • Derive simplified Boolean expressions (K-map or equivalent). • Draw a clean logic-gate schematic. • Produce a working simulation in Logisim and deliver matching VHDL code so I can integrate it later. Other tasks: 1-study state 2-truth table 3-K-maps 4-log...

Design and implement a basic 8 Bit CPU on an FPGA board The implementation will use Verilog (or VHDL if preferred) and target a standard, widely available FPGA board like the Xilinx Coartex-A7 ensuring compatibility with Vivado. Deliverables • HDL source: well-commented modules for datapath, ALU, control unit, registers, and memory interface • Testbenches: simulation covering each instruction, plus a self-checking program counter/ALU regression • Vivado artefacts: implemented design, timing summary, resource utilisation report • Schematics: readable datapath and control diagrams (PDF or PNG) • Documentation: 4–6-page write-up describing micro-architecture choices and verification plan • Bitstream + demo program: ready-to-flash ...

... get the controller blocks synthesised, and prove they behave identically once they’re running on silicon. Sensor integration and data logging can wait; the immediate focus is control-algorithm work and, in particular, thorough algorithm testing after it lands on the chip. Deliverables • Partitioned Simulink model with the guidance/control section prepared for HDL Coder • Synthesizable VHDL/Verilog project targeted to the DE2-115 and built in Quartus • Configured Simulink FIL interface (JTAG link, board files, timing setup) • Automated test bench in Simulink that compares host versus FPGA outputs and confirms fixed-point accuracy • Short, clear setup guide so I can reproduce every step on my own machine Acceptance criteria The c...

Assalam o alaikum, I am lo...simulation and report writing with zero plagiarism. (use of chatGPT highly prohibited). I am looking for experts who can deal FYP related to following domains of electrical engineering: Power Systems / Renewable energy systems Control Systems Signal Processing Instrumentation Engineering Internet of things Freelancers must be proficient with following: • Arduino/Raspberry Pi • FPGA | Verilog/VHDL • Proteus | TinkerCAD • Multisim | LabVIEW • MATLAB/SIMULINK & Python ***MOST IMPORTANT*** Applicants should be proficient in technical report writing and must have good command over proper formatting of final year reports by following their templates provided by different universities. Reports shoul...

...storytelling. The Role: We’re seeking a full-time direct report who is both a skilled FPGA developer and a creative marketer. You’ll be responsible for building FPGA learning content, engaging our community, and driving growth across multiple digital channels. Core Responsibilities: - FPGA Development & Content Creation (blogs, technical articles, demo projects) - Hands-on Verilog design (other HDLs like VHDL, SystemVerilog a bonus) - Create FPGA learning blogs, tutorials, and educational resources - Develop demo projects and showcase them in accessible formats Digital Marketing & Community Engagement - Run newsletters and manage a content calendar - Write clear, engaging technical articles in excellent English - Manage so...

I’m pushing a fast-turnaround project and need another pair of expert hands. The goal is a small, custom CPU core—built purely in Verilog or VHDL—tuned for signal-processing tasks and proven on a Xilinx board you already have running on your bench. I’ll supply the high-level instruction set, throughput targets, and the specific signal operations I need accelerated. You’ll translate that into a synthesizable design, simulate it, meet timing, and show it running on your board so we can iterate in real time. Deliverables • RTL source (Verilog or VHDL) • Simulation test-bench with passing waveforms • Synthesized design for a recent Xilinx family (Vivado project or equivalent) • Resource and timing repor...

Note: The project must include code, schematics, and a short technical write‑up. ● Design a basic CPU (even 8‑bit or a minimal RISC‑V subset) in Verilog/VHDL, implement it on a low‑cost FPGA board, and run a small instruction set or demo program, emphasizing microarchitecture choices and timing closure. ● Deliverables: HDL source, timing/area reports, simulation testbenches, and a brief report on design methodology and verification strategy. ● Mixed‑signal sensor acquisition front‑end Note: The project must include code, schematics, and a short technical write‑up.

Aqui está uma sugestão de descrição de projeto, otimizada para publicação em uma plataforma como a Freelancer.com, com base no documento que você forneceu. Título da Vaga Projetista VHDL/Verilog para Processador MIPS 32-bits (Pipeline e Cache) Descrição Completa do Projeto Estou buscando um desenvolvedor experiente em VHDL ou Verilog para completar um projeto acadêmico de arquitetura de computadores. O projeto é dividido em duas partes principais, e o freelancer deve entregar ambas as partes para a conclusão do trabalho. O objetivo é projetar e implementar um processador MIPS de 32 bits, começando com um design básico e, em seguida, evoluindo-o para u...

I need a VHDL IP core that sits between two AXI4-Stream FIFOs, ingests a packet of N values, performs a simple arithmetic tweak, and pushes the result back out. Here is the exact scope: • Interface: one AXI4-Stream slave for input, one AXI4-Stream master for output. • Packet size: parameterised (e.g. default 8 words, 32-bit each). • Operation: addition with a constant, hard-coded inside the source (no run-time configuration needed). • Overflow handling: if more than N words arrive before TLAST, raise a dedicated error line and discard the surplus. • Deliverables: – Readable, synthesizable VHDL source for the core. – A self-checking test-bench (ModelSim/Questa or similar) that drives typical and corner-case traffic, shows t...

...constraints file (SDC) handling clock, IO delays, and false/multicycle pathsPower planning and optimization for low power operation (optional if applicable)Final GDSII or layout database for tapeout or further place-and-route stepsTiming reports demonstrating timing closure with specified constraintsVerification of design correctness via post-layout simulation support files (optional)Provided Files:RTL Verilog sources for SPI, I2C, UART modules, and the top-level Multi-Protocol Conversion Unit (mpcu_all.v and associated testbenches)Protocol conversion logic (conv_protocl.v)Research and design analysis paper ("")Sample SDC constraints file (can be enhanced/modified as per target technology)Constraints and Environment:Clock frequency:

I’m planning an automotive-grade ASIC focused on reliable sensor interfacing and need a seasoned embedded engineer to shape the initial blueprint. Here’s what I’m looking for: • A high-level architecture that defines power domains, I/O pinout, and core logic blocks dedicated to sensor data acquisition. • Block-level Verilog or VHDL stubs for the key sensor interface modules so I can validate feasibility on my end. • Basic timing, power, and temperature estimates suitable for an automotive environment (-40 °C to 125 °C). • A short BOM or technology recommendation—foundry node, package type, and any external components essential for stable operation. Keep the scope to this early concept stage; I’m not seeki...

I need a Verilog implementation of a CNN accelerator with a DRAM interface. The accelerator should perform matrix multiplication on fixed-size matrices. The DRAM interface should be DDR3. Key requirements: - Functionality: Matrix multiplication only - Matrix type: Fixed-size matrices - DRAM interface: DDR3 Ideal skills and experience: - Proficiency in Verilog - Experience designing CNN accelerators - Knowledge of DRAM interfaces, specifically DDR3 - Strong background in digital design and hardware description languages Please provide relevant experience in your bids.

I’m looking for a clean Verilog design that realises a 3-bit synchronous counter, counts in ordinary binary from 0 through 7, and drives a single seven-segment display mounted on a Zynq MP FPGA board. Everything will be built and programmed inside Xilinx Vivado, so please target the standard Zynq MPSoC constraints and make sure your files open and synthesise without warnings there. What I need from you is the complete module for the counter itself, the segment-decoder logic, a concise test-bench that proves the 0-to-7 sequence, and a Vivado project or clear instructions that allow me to generate the bitstream and dump it straight to the board. Timing must be synchronous to the on-board clock, and resets should be active-low so I can link them to a push-button. Acceptance cri...

I need a concise, synthesizable Verilog finite-state machine that detects the bit sequence 1011 (with overlap) and drives a single-cycle “found” pulse when the pattern appears. The design must target a Xilinx Zynq board and be built in Vivado 2022.1. Please use binary state encoding; that choice is fixed for this job. Here’s how I’d like the work delivered: • Source files: top-level Verilog module, separate testbench, and any support files. • Constraints: an XDC pinout I can adapt to my board. • Vivado 2022.1 project archive, including synthesis and implementation reports. • Generated .bit file so I can program the FPGA immediately. • Short read-me explaining the state-transition diagram, how overlap is handled, and h...

I have to count very fast digital pulses—up to 200 MHz—using a Xilinx XC7S50 (Spartan-7, BGA package). The design must implement four independent 64-bit counters that share a common asynchronous reset line brought out to a single input pin. Read-back of the counts will happen over an SPI link, so the HDL should expose a simple, register-mapped SPI slave. Alongside the synthesizable VHDL or Verilog, I also need practical guidance on the hardware: how to lay out or select a compact development board that suits the XC7S50, ensures the 200 MHz signal integrity, and brings out the reset and SPI pins cleanly. If an off-the-shelf board will work, point me to it; if a custom carrier is wiser, outline the critical constraints (clocking, decoupling, pin assignments, oscill...

...from the following building blocks: • Operational Amplifiers (Op-Amps) • Digital-to-Analog Converters (DACs) • A Howland Current Pump topology If you have a more elegant approach that still meets the accuracy requirement I’m open to hearing it, but the solution must remain feasible for small-batch assembly. Deliverables • Complete walkthrough of how to connect components to FPGA • Verilog/VHDL code for the FPGA, including a simple register map that lets a microcontroller or PC set each channel’s current (positive or negative) and trigger synchronous updates. • Well-commented simulation files showing stability of the analog loop and timing closure in the FPGA. I will provide the desired mechanical outline for the...

... Deliver source code, firmware binaries, and short documentation. Ensure the firmware enumerates correctly and interacts properly with test drivers. Deliverables Working firmware image for 100t/75t target. Source code + build instructions. Brief test report confirming CFG, BAR, and DMA functionality. Skills Needed Strong knowledge of PCIe / DMA / BAR / MSI-X / Verilog / Vivado. Experience with embedded C/C++/Verilog and firmware development and Vivado Firmware Development. Familiarity with FPGA-based PCIe devices (Xilinx or similar) is a plus. If you can fulfill this project I will possibly use you for 3 other similar projects. Legal Notice This project is strictly for legitimate driver testing and research use — not for bypassing security or anti-chea...

I need a compact DVB packet processor written in Verilog that runs on a Lattice iCE40 FPGA. The sole task is packet filtering—specifically PID filtering—restricted to one selected PID at a time. Scope • RTL design in clean, synth-ready Verilog targeting the iCE40 HX or UP family • Functional testbench that feeds 188-byte TS packets, demonstrates correct acceptance of the chosen PID, and drops everything else. • Synthesis script (nextpnr + IceStorm or Lattice Radiant) showing timing closure at 27 MHz TS clock or better. • Resource-usage report so I can judge fit against the device’s limited LUT/BRAM budget. • Simple register or constant that lets me change the target PID before build time; run-time reconfiguration via a sm...

... Deliver source code, firmware binaries, and short documentation. Ensure the firmware enumerates correctly and interacts properly with test drivers. Deliverables Working firmware image for 100t/75t target. Source code + build instructions. Brief test report confirming CFG, BAR, and DMA functionality. Skills Needed Strong knowledge of PCIe / DMA / BAR / MSI-X / Verilog / Vivado. Experience with embedded C/C++/Verilog and firmware development and Vivado Firmware Development. Familiarity with FPGA-based PCIe devices (Xilinx or similar) is a plus. If you can fulfill this project I will possibly use you for 3 other similar projects. Legal Notice This project is strictly for legitimate driver testing and research use — not for bypassing security or anti-chea...

I’m building a simple digital-lock proof-of-concept on a Nexys Artix-7 board using Vivado. At this stage the only feature I need is a basic lock-out mechanism—no fingerprint, keypad, or card reader yet. I already have a rough plan and can handle the introductory VHDL/Verilog myself, but I want an FPGA expert to: • Review and refine my high-level design so the lock-out logic is clean and synthesizable. • Supply or polish compact, well-commented code blocks where my initial draft falls short. • Walk me through synthesis, implementation, and on-board testing in Vivado, stepping in to debug timing or constraint issues that pop up. I’ll run the hardware on my end; you’ll provide guidance via chat or quick screenshares and, when necessar...

We are looking for a skilled FPGA Design Engineer with solid experience in VHDL development and FPGA toolchains (Vivado, Quartus). You will collaborate remotely using our servers and follow a structured workflow that includes version control, automated analysis, and verification. The ideal candidate is proactive, detail-oriented, and comfortable working on real FPGA design tasks, from module development to system-level integration. Responsibilities Design, implement, and verify VHDL modules for FPGA-based systems. Work with Xilinx (Zynq) and Intel (Altera) FPGA platforms. Integrate and debug high-speed serial protocols such as Aurora, SDI, HDMI, 10 GbE, and other Gbps transceiver-based links. Support signal processing and video processing implementations on FPGA. Contribute...

...existing RISC-V core and dramatically speeds up convolutional layers in a CNN inference pipeline. The sole metric I care about is throughput: higher frames-per-second at the same clock. Power savings or memory tweaks are nice side effects, but raw speed is what will decide success. Target platform is an FPGA prototype, so the RTL should be synthesis-ready and resource-aware. I am comfortable with Verilog, VHDL, SystemVerilog, as long as the code is clean and well-documented. AXI4 or an equally common on-chip bus is expected for host interaction, but I’m open to your suggestion if it fits the RISC-V ecosystem better. Key points you should hit • A custom instruction or tightly-coupled accelerator port on the RISC-V CPU for launching 2-D convolutions. • ...

...digital circuit design and we’re looking for an ECE-trained partner who can jump in quickly. The work ranges from drawing clean schematics and selecting ICs to running simulations and walking us through timing or power considerations before we commit to the board. Typical tasks you might handle include: • Translating our functional block diagrams into gate-level or HDL implementations (Verilog/VHDL welcome). • Producing simulation files and screenshots that prove the logic works (Multisim, Proteus, Quartus, ModelSim—whatever you are comfortable with). • Supplying concise notes so the rest of the team can reproduce or extend the design. If you have breadboard or FPGA experience and can show a quick demo video, that’s a bonus but ...

...Once the high-level structure is solid I will extend the effort into detailed logic-gate diagrams and the encoding of every operation, so choices made now must scale. Here is what the finished package should cover: • Block-level architecture diagram that shows ALU, registers, control unit, I/O and clock domains. • Signal-flow description (timing, control, data) clear enough to drop into VHDL / Verilog or a schematic capture tool. • Instruction or operation encoding table that unambiguously links op-codes to control word bits. • Written rationale for design decisions and resource estimates (gate count, memory, timing margins). • Any simulation or verification artefacts that prove the arithmetic units behave correctly. Submit a detailed pro...

I need an experienced FPGA developer to design, program, and test an SDI fiber converter. The converter should support video signal conversion for HD-SDI and 3G-SDI formats. It must have SFP and SDI input & output i...conversion for HD-SDI and 3G-SDI formats. It must have SFP and SDI input & output interfaces. Key Requirements: - Design and implement video signal processing algorithms - Program FPGA to handle HD-SDI and 3G-SDI formats - Integrate fiber optic and SDI output interfaces - Thorough testing to ensure reliability and performance Ideal Skills and Experience: - Proficiency in FPGA programming (Verilog/VHDL) - Experience with video signal processing - Knowledge of SDI and fiber optic interfaces - Strong troubleshooting and testing skills Looking for high-qu...

I need a clean, Segmened Analysis and Necessity first search algorithm implementation using python then reduced coefficients constants will be given as input to rmcm block as hardcoded values in Verilog well-structured Verilog implementation of an FIR filter that follows the RMCM (Reconfigurable Multiple Constant Multiplication)architecture. The goal is strictly functional verification, so everything happens inside ModelSim; no FPGA bitstream or ASIC sign-off is required. The code must be synthesizable, but the only deliverables I need at this stage are: • Verilog source files that realise the RMCM-based FIR • A self-checking ModelSim test-bench with a small set of example input vectors and expected outputs • Simulation snapshots or log files that ...

...variety of ongoing and upcoming projects. If you're passionate about solving real-world engineering problems and want to work with a dynamic, growing team, this is your opportunity! Areas of Expertise We’re Looking For: We welcome experts in any (or multiple) of the following domains: * ✅ Digital Electronics * ✅ Power System Analysis * ✅ MATLAB / Simulink * ✅ ETAP * ✅ PowerWorld Simulator * ✅ Verilog HDL * ✅ FPGA Design & Simulation What You’ll Do: * * Collaborate with our in-house engineers on project-based tasks * Deliver simulation, analysis, and modeling results * Optimize systems for real-world application * Work *remotely* and communicate via online tools *Requirements: * * Proven experience in one or more of the tools/areas listed above * Abili...

I have a digital down converter that decimates by 2 in VHDL for my final degree project, i compare the output with matlab fixpoint i am not able to get error zero,i guess the problem is the filter_semi_par architecture that doesnt work good,i need someone to check it and help me,the principal project is ddc_semi_par the other project is for debbug alone better if you want it the filter_semi_par architecture You’ll find a ZIP in the repository that contains: • the full project scripts and codes , • a clean, stand-alone version of the semiparallel module for faster iteration, • a small testbench that compares fixed-point results against the float-point reference. What I need from you is a precise, reproducible fix: 1. Identify why the semiparallel implem...

...runs on an Artix-7 FPGA and lets me capture analog signals up to about 50 MHz from 6 x AD9226 12 bit ADC's simultaneously . The goal is simple: store every sample intact to DDR3 for 500ms, and make the stored data available later by QSPI at 40MHz, or USART. Use one digital input as trigger to start AQ, one to erase full DDR3, one to select QSPI or USART. Scope of work • Build the RTL (VHDL or Verilog—your choice) that interfaces the FPGA with a suitable high-speed ADC, brings the samples into the fabric, and buffers them without loss. • Implement a storage path—on-chip BRAM, external DDR3—to hold the data until I pull it off the board. • Provide a clean, documented interface (for example QSPI, UART, USB FIFO) that I can use from...