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    4,397 verilog vhdl punët e gjetura, me çmimin EUR

    Hello, Everyone I am looking for VHDL expert for vhdl register without using process. Will discuss more details with expert only. Thanks

    €125 (Avg Bid)
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    7 ofertat
    Library for asic 8 ditë left

    We need to make a library for Asic and testing Verilog code into it

    €530 (Avg Bid)
    €530 Oferta mesatare
    1 ofertat
    test-bench for VHDL module 4 ditë left
    VERIFIKUAR

    I need the test bench working with modelsim to validate the module has been written in vhdl. The test bench needs to check the working stage of module.

    €14 / hr (Avg Bid)
    €14 / hr Oferta mesatare
    11 ofertat

    microcontroller programs employing peripherals ADC and PWM peripherals Scheduling and concurrency using FSM RTOS Wireless systems and IoT State machines( Verilog) Digital Design using Verilog and software Programming FPGAs Embedded processors

    €211 (Avg Bid)
    €211 Oferta mesatare
    19 ofertat

    Would like someone who can code in verilog-A for TFET within limited time

    €104 (Avg Bid)
    €104 Oferta mesatare
    2 ofertat

    Looking for help on an adder project in verilog

    €21 (Avg Bid)
    €21 Oferta mesatare
    11 ofertat
    System Verilog Project -- 2 16 orё left
    VERIFIKUAR

    Hi, I am looking to optimize my current system verilog code. Please let me know if you have experience implementing optimization techniques in System Verilog.

    €23 (Avg Bid)
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    11 ofertat

    Hello, you've sent me a message earlier about a project in Xilinx and VHDL, are you still available?

    €60 (Avg Bid)
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    1 ofertat
    Verilog Project in MODELSIM Ka përfunduar left

    Modul de inmultire, folosind sumator si registrii de deplasare

    €107 (Avg Bid)
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    11 ofertat
    Verilog Project Ka përfunduar left

    I have a project about implementing a Datapath and a Controller FSM for Fibonacci Series Calculator on Quartus and Modelsim.

    €25 (Avg Bid)
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    9 ofertat

    Need someone to Recheck my Verilog Code for PipelineDesign

    €83 (Avg Bid)
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    5 ofertat

    I am looking to hire someone to go through the vitter algorithm of the dynamic huffman coding and implement the encoder(compulsory) and decoder(optional) . I am willing to explain you the details of the algorithm in depth once we connect . there are several articles that I have referred to but the wikipedia description is pretty accurate so I provide the link here. There is a visual representation of the same algorithm in the other links and some accompanying text explaining. You are required to go through the vitter algorithm and implement the same. Links : 1) 2)

    €121 (Avg Bid)
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    4 ofertat
    €80 Oferta mesatare
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    I have written the code for a simle SPI Master in verilog and also included a testbench. I want you to: 1) Add a Clock Divider to it, so that the output SPI frequecy is 1MHz 2) There are 3 SPI commands: (1) one write command, (2) multiple write command, (3) one read command. Modify the SPI master Verilog code to implement these 3 commands. Ideally, I want to specify (i) write or read, (ii) number of bytes if write command, (iii) address, (iv) data, then the code will automatically generate the correct checksum and dummy bytes. Would appreciate if the work could be finished as soon as possible. Thanks!

    €8 (Avg Bid)
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    5 ofertat

    2 interface accessing the arbiter through clock crossing using a config register. More details will be shared later.

    €20 (Avg Bid)
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    6 ofertat
    Computer Architecture Ka përfunduar left

    Need to code in ARMv7 and VHDL. Questions would be tough

    €88 (Avg Bid)
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    6 ofertat
    Need help with VHDL Ka përfunduar left

    Need help to code for a hamming coder. Please let me know if you can do it.

    €18 / hr (Avg Bid)
    €18 / hr Oferta mesatare
    7 ofertat

    i have a code for tfet using verilog-a,i need to get a circuit from verilog-a in cadence virtuoso and design digital circuit,half adder and ring oscilator

    €17 (Avg Bid)
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    3 ofertat

    Design, simulate and verify a synchronous digital system that detects and recognizes your student ID as password that can be used to generate an output signal. The student ID is entered to the system sequentially and synchronized to the master clock for proper operation of the system. The system is expected to generate an output logic High for 3 clock cycles if the ID sequence is detected correctly. The system will then return to the wait state, where it waits for a new sequence to be entered by user. Use any of the student ID from the group members in this design. You are free to add any additional features to your system as deemed appropriate.

    €4 / hr (Avg Bid)
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    10 ofertat

    I need someone expert in python and Verilog/VHDL

    €138 (Avg Bid)
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    9 ofertat
    FPGA Image processing -- 3 Ka përfunduar left

    hi i want to create one image processing code for attached images . final image has different. This small dot can be any where in this white line . can you do this? code should have to find this dot in blue red ,yellow etc apart from can use only Verilog or VHDL here please send your price for this and time . Then we can start.

    €601 (Avg Bid)
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    5 ofertat

    , I need help with, Single cycle data-path design of CPU with assembly code in Verilog.

    €217 (Avg Bid)
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    4 ofertat
    I need help -- 2 Ka përfunduar left

    Hi, I need help with, Single cycle data-path design of CPU with assembly code in Verilog.

    €7 - €21
    €7 - €21
    0 ofertat
    Need VHDL Expert Ka përfunduar left

    Need a VHDL Expert designing processors

    €91 (Avg Bid)
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    8 ofertat

    Need an expert in VHDL with Microprogrammed control unit and hardwired control unit design for a 1 bit processor

    €82 (Avg Bid)
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    8 ofertat
    Verilog expert needed today Ka përfunduar left

    Message me for more info about the project.

    €115 (Avg Bid)
    €115 Oferta mesatare
    18 ofertat

    Need to implement neural network testing on verilog. Need verilog coding. Training and testing done in matlab. And then testing part again done in verilog. And then compare the computational time of matlab and verilog

    €59 (Avg Bid)
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    1 ofertat

    I need help to Define a transmitter module in Verilog using VHDL. I will provide more details in chat.

    €71 (Avg Bid)
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    11 ofertat
    I need a VERILOG EXPERT Ka përfunduar left

    Verilog needed for this project. A developer to work quick

    €29 / hr (Avg Bid)
    €29 / hr Oferta mesatare
    4 ofertat
    Lattice_CPLD_verilog Ka përfunduar left

    Need help with Lattice CPLD Verilog design - - simple power sequencing, GPIO registers control, I2C, RS232

    €2776 (Avg Bid)
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    13 ofertat

    Design an 8 bit microprocessor in VHDL with two execution stages: fetch and execute. There are two shared buses, one for address and one for data. Both the buses are connected to an external memory. There is a pdf attached which provides a more information and the expected structure of the microprocessor. Any other questions please ask in chat.

    €124 (Avg Bid)
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    6 ofertat

    Digital designs, circuits and designs. i need help with some questions

    €18 (Avg Bid)
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    5 ofertat

    These are just 3 simple questions needed to be completed on the topic of sequential circuits in Verilog. I have to submit this in 2 hours, so if you can do it quickly please accept this offer it is very simple.

    €13 (Avg Bid)
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    3 ofertat

    Control DC motor by pulse frequency modulation (PFM) IN VHDL . I want code and testbench for Dc motor pwm by vhdl and using fpga Model of fpga kit ( DE10-Lite) End of the project I need a report

    €36 (Avg Bid)
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    5 ofertat

    Top cell : alu I/O: bit 15 is the most significant bit. INPUTS: A(15:0) , B(15:0) , alu_code(4:0) ; OUTPUTS: C(15:0) overflow TOP MODULE: 16-bit Adder Module PRIMARY SIGNALS: BUS inputs/outputs and additional signals BUS signals: bit 15 is the most significant bit. All bus signals are named with upper case letters INPUTS: A[15:0], B[15:0],CODE[2:0] OUTPUTS: C[15:0] More details in Chat!

    €107 (Avg Bid)
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    15 ofertat

    We are a research gr...working human study involving debugging assistance for Verilog designs. The study involves asking designers to debug mistakes in circuit descriptions, either with or without some form of debugging assistance. The debugging hints can take the form of highlighting the wire or register name with the bug, or highlighting several lines of code likely containing the bug. We are hoping to figure out what forms of debugging assistance work best in helping hardware designers fix mistakes efficiently, and eventually hope to integrate our findings into a learning tool aimed at teaching novices how to write Verilog descriptions. The study is expected to take around 45 minutes to an hour to complete, and we will compensate people familiar with Verilog $25 for...

    €9 - €27
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    I need VHDL Designer Ka përfunduar left

    This is a final year project. We are struck with simulation. Need to debug our program, or else develop the project from scratch. I am attaching the code that we have wrote for your reference. We used Quartus altera for coding, and model sim for simulation. The development board is a cyclone 2. There were no errors as such. The code would simulate and after one clock cycle, the output would become 'Z'. From what I understood, the main issue is the interconnection between all the modules.

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    i have design some circuits and i need implement using magic also need test using irsim from () i have a pdf file to describe everything you should do , text me for more .

    €191 (Avg Bid)
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    I need a pwm generator for vivado 2020.2 running on a zturn board 7020, complete of tcl scripts for ip creation, sim files and constraints

    €190 (Avg Bid)
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    5 ofertat
    VHDL Designer Ka përfunduar left

    This project requires the student to implement a 10-bit counter design using VHDL. The counter will have the ability to count up and down from 0 and 1000. This requires the utilization of 16 slide switches and the center push button of the Basys3 board. The 10 right-most switches (SW0 – SW9) will be used to input a preset value to the counter or the ALU. SW0 represents the LSB and SW9 represents the MSB of the input value. The center push button (BTNC) is used as the manual clock for the counter. The count should increase or decrease (depending on the selector switch, SW13) by 1 on every rising edge of this button.

    €134 (Avg Bid)
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    VHDL multiplexer code Ka përfunduar left

    Using ISE design suite. Design an 8-Bit ALU (x and y are inputs and Result is output), based on modular arithmetic and logic circuits and 8x1 line multiplexer, in VHDL. Add comments to your code whenever required. Design a test bench to verify your designed circuit functionality. Add simulation results screen shot. ** I will share more details if you will do it

    €44 (Avg Bid)
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    3 ofertat
    VLSI VHDL OR VERILOG Ka përfunduar left

    Implement your design using Magic VLSI layout tool to generate your project layout Test your design using irsim to simulate your project. Reqired Magic VLSI tool is running on ubuntu OS SRAM PROJECT VLSI

    €133 (Avg Bid)
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    4 ofertat

    I need help with my project. You must be good at RISC-V and Verilog. The project is related to Cache. Please check the file

    €24 (Avg Bid)
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    i need help in Implement MIPS processor pipeline and instruction and data caches, using VHDL. i will provide more details in the chat.

    €44 - €45
    €44 - €45
    0 ofertat

    hi everyone, I need a fractal image compression code (for a 128*128 image) implemented on a DE2 cyclone II in the M4K memory which has 105 blocks.

    €126 (Avg Bid)
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    3 ofertat

    This is a simple project in Verilog using System Verilog features as well. We are given the base sv file with a testbench as well, we just have to complete the file with the required code to complete the project.

    €22 (Avg Bid)
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    1 ofertat

    write codes and the screenshot of your schematic in a text file. Then you have to make a video presentation

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    4 ofertat
    Verilog/VHDL Ka përfunduar left

    I need a person who can do verilog

    €17 / hr (Avg Bid)
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    7 ofertat
    FPGA4student Ka përfunduar left

    This VHDL project is to design and implement noise filtering, metastabiliy and synchronization of given signals

    €196 (Avg Bid)
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    5 ofertat