Verilog vhdl punët

I am an EE engineer. I have lots of experience designing both a...language and C/C++ (both procedural and OOP). *for STM and nrf controllers Mbed OS could be one of the choices for programming the MCU. I have done lots of projects in the field of wireless communication and IoT using different wireless communication protocols like BLE, RF, WiFi (Cloud), etc. In the field of bit streaming, high-speed processing and ML, I am able to program both Xilinx and Altera in VHDL or C/C++ for Microblaze or NIOS II processors. For manufacturing purposes, I can provide component selection and BOM which suits your needs for a durable, efficient, and effective design. ABOUT YOUR PROJECT, I have done lots of similar projects before and can handle your project easily. We may discuss it more over cha...

I am looking for a skilled professional to design a fast division circuit with a required speed of less than 1 nanosecond. The technology that should be used for the circuit design is Verilog. As for specific requirements or limitations, I am open to suggestions and willing to work with a creative and experienced freelancer who can suggest the best solutions for this project. Ideal skills and experience for the job include proficiency in circuit design, experience in using Verilog, and the ability to work efficiently to meet a tight deadline.

We are looking for a skilled developer to create a webpage for code generation. The ideal candidate should have experience in web application, web design, and web development. The webpage will be used to generate VHDL modules for FPGA. The user will input certain parameters, and the webpage will output the corresponding code. The interface needs to be user-friendly and easy to navigate. We want to be able to add new modules, and the background code generator is already developed by us (Tcl scripts). The candidate shall propose a way to interface between the webpage and the Tcl script that generates the code. To apply for the position, please submit a detailed proposal outlining your experience and how you can help with the project. Please include links to past completed projects ...

First of all all the requirements on project documentation needed I am looking for a freelancer to help with the implementation of a single-cycle MIPS processor. The ideal candidate should have experience in digital logic design and computer architecture. The project requires the f...client in project documentation. Documentation: - The client requires in-depth analysis with diagrams in the documentation. - The documentation should cover all aspects of the implementation process, including design, testing on ModelSim simulator, and verification. Skills and experience: - Digital logic design - Computer architecture - Experience with MIPS instruction set - Experience with Verilog or HDL -Experience with ModelSim simulator The freelancer will be required to provide regular updates on...

We need support for TCL scripting, FPGA projects. Tcl sripts will be used to compile and simulate VHDL code, synthesize, P&R and analyze reports

Campera Electronic Systems is planning to introduce a Verification methodology in the company verification flow for VHDL designs. Previous experience on one of the "standard" VHDL verification methodologies (UVVM, OSVVM) or framework (Vunit) is requied.

I am seeking a VHDL expert to help me implement a control system using VHDL. The purpose of this project is to implement a control system, and the specific type of control system has not been specified. The ideal candidate will have experience with VHDL and control systems, and be able to work efficiently and accurately. Please provide examples of previous VHDL projects you have worked on.

I am seeking a technical writer and system improvement expert to help me with my project. Specifically, I need help with improving the software aspect of the system which includes C, Vivado, Python, and Ethernet. The ideal candidate should have experience with VHDL and ZedBoard at an intermediate level. The following skills and experience are required for this project: - Technical writing for system documentation - Knowledge of software (C, Vivado, Python, Ethernet) - Intermediate experience with ZedBoard and VHDL If you possess the above skills and experience, please apply for this project.

I am seeking a VHDL expert to help me implement a control system using VHDL. The purpose of this project is to implement a control system, and the specific type of control system has not been specified. The ideal candidate will have experience with VHDL and control systems, and be able to work efficiently and accurately. Please provide examples of previous VHDL projects you have worked on.

I am looking for an experienced Verilog or VHDL engineer to help me explain and design Number theoretic transform (NTT) which is the most efficient method for multiplying two polynomials of high degree with integer coefficients, using FPGA. The project has specific requirements and I will provide detailed specifications. The desired implementation platform is Xilinx FPGA using Vivado and the deadline for the project is 1-2 weeks. Ideal skills and experience for the job include Verilog or VHDL programming, FPGA design, and NTT knowledge.

Hello! I have 4-5 codes. available online. some of them have verilog and testbench codes. and some doesnot have the testbench. So, I need: I will apply the completed codes in my laptop, and if there is any error help me in fixing them. write the testbench codes if it does not found. helping me in understanding the codes I set 5 dollars for each completed codes (verilog,testbench) thanks

I have 5 verilog codes some of them need to write testbench and the others already have. The tasks: Help me in runing the codes, modifiing them if there is any errors. Write the testbench codes when needed Helps me in understanding the codes. No of coeds 5 I have the free source for the codes

Verilog Simulation and Testbench Modification Project I am looking for a freelancer who can assist me with a Verilog simulation project. Specifically, I need someone who can modify an existing Verilog code to create a basic level testbench. I have two codes: Clock divider, 7segemnt, and I need to apply them Required Skills and Experience: - Strong proficiency in Verilog programming language - Experience with Verilog simulation and testbench design - Familiarity with ModelSim tool or equivalent - Ability to communicate effectively and work collaboratively If you have the necessary skills and experience, please apply for this project.

how to program a microcontroller to read the room temperature from a sensor and control a DC motor, which is connected to a fan and also required to design a random access memory device in VHDL for the microcontroller.

Simulation and implementation of two players pong game under some constraints in Verilog.

Implementation of a Moore finite state machine with 2 - 4 D-FlipFlops simulating a control system. Design.v and testbench.v needed.

We are seeking a VHDL FPGA programmer to develop a program for data encryption and decryption with a high level of security. The ideal candidate should have experience in VHDL programming, FPGA design, and encryption/decryption algorithms. Functionality: - The program should provide high-security data encryption/decryption that meets the client's requirements. Encryption/Decryption algorithms: - The client needs suggestions for encryption/decryption algorithms that meet their high-security requirements. The ideal candidate should have experience in suggesting and implementing secure encryption/decryption algorithms. Level of security: - The client requires a high level of security for the encryption/decryption process. The ideal candidate should have experience i...

I will implement it in one week

I am looking for an experienced freelancer to work on an FPGA based project. The main goal of this project is performance optimization, and I am looking for someone with experience using the Xilinx platform, and coding in VHDL. I am looking for someone who can ensure that the project turns out as expected and meets all my requirements. Additionally, I would like the outcome of this project to have a positive impact on my organization's performance. The freelancer I choose must have in-depth and up-to-date knowledge of the FPGA architecture as well as memory control, interfaces, and system design. He/she should also possess excellent programming experience and be able to provide detailed reports and documentation in a timely manner. Moreover, I need assurance that this project...

Expand on the design of a single-cycle RV32I processor core called Archer, which implements most instructions of the RV32I base integer instruction set. Your the task will be to pipeline the processor and add hardware support for data forwarding and hazard detection.

Hello, I need code that turns on an 80% duty cycle when the feedback voltage drops below 1.5 V. I also need the voltage to be displayed on a LCD display. I need it coded in verilog to work with a DE-10 lite board.

Project for a simple security system design in System Verilog code, design and testbench.

I am looking for someone to develop a project that will allow data to be transmitted from my Field Programmable Gate Array (FPGA) to a PC. The connection type that should be used is USB and the language used to communicate must be Verilog. Data that needs to be transmitted is text only. I need a detailed solution that can handle transmission of data in a smooth, consistent manner. It should be able to identify events and their associated data while being reliable and efficient. The hardware and software involved should be thoroughly tested and debugged. The solution should also be documented and include any necessary reports/specifications. The project should be delivered in a timely fashion.

I am looking for a freelancer to design a single clock process based on RISC-V ISA using Verilog. The clock process design must have the following specific features and functionalities: The project only requires the implementation of the base RISC-V ISA, without any specific extensions. The ideal freelancer must be skilled and experienced in Verilog and have a deep understanding of RISC-V ISA. Additionally, I would prefer someone who has previously worked on similar projects and can provide examples of their work.

Soy un estudiante de ingeniería electrónica que necesita aprender VHDL, XILINX y dsp. Busco alguien que pueda crear un conjunto de tutoriales en vídeo, audio y texto para ayudarme a debugear y escribir código. Estoy buscando tutoriales y clases para diseccionar y detallar algunas aspectos de un proyecto Estoy ansioso por encontrar alguien para ayudarme a que logre mis metas de aprender estás herramientas y que me sienta a gusto cuando they llegue la hora de aplicarlo.

I am looking for a freelancer who can help me find a behavioral module that incorporates all of the methods used to implement true addition and true subtraction with a test bench module. The ideal candidate should have experience in Verilog and be able to work on a project with some design preferences. The test bench module should have a basic level of complexity.

I am looking for a freelancer to design a gas detector circuit using Verilog for the Basys 3 board. The detector should be able to sense Carbon Monoxide gas. I have a rough idea of what I want. The buzzer alarm does not have any specific requirements, but it should be loud enough to be heard. The ideal skills and experience for this job include proficiency in Verilog, knowledge of gas detection circuit design, and experience with the Basys 3 board.

I need to control the buck converter using a current mode control in digital form. That means i need to use digital PI, ADC converter, Digital PWM. For these digutal controlling parts I have to write verilog codes or have to use IP's in vivado to implement on FPGA. At the end I need to do PCB design for the buck converter and after that I have to combine them and observe the results on oscilloscope.

Hello! I am in need of a freelancer to help me with a project creating a car elevator controller. The controller will be created using Vivad Verilog code and fpga implementation. I am looking for someone who can provide a detailed project proposal in their application. It is also important they have past work and experience in the same field. I won’t need any type of remote access for this project so please do not include any advice on that as part of your proposal. If you believe you are suited for this project and would be interested in working with me, please apply and include your detailed project proposal. I look forward to hearing from you!

I am looking for help with creating a System Verilog code for a sequential multiplier and a floating point multiplier. For the multiplier, I would need both types: sequential and floating point. The verification of the functionality is required. I am necessary looking for an experienced engineer who truly understands what's needed for this requirement and can efficiently and quickly develop the code for it.

As part of a development project, I need help designing verilog code on Xilinx. I'm looking for experienced freelancers with the technical skills to properly implement the design. I need complete control when it comes to providing feedback and making sure the progress is on track. The right candidate should have a solid track record and demonstrate their expertise in the same field before applying to the job.

Proyecto en xilinx empleando VHDL, clases y verificación de códigos

I have a task in VHDL looking for VHDL code to control Epson printhead.

I'm looking for a VHDL 1st-in 1st-out (FIFO) project to be completed. I need a Verilog code to complete the FIFO example. Also, syntax is very important, therefore, I am attaching an example (LIFO) to illustrate the syntax.

write a verilog code for a straight line equation y=mx+c where all m,x and c are 32 bit and even after arithmetic operations between m,x,cand y the final values should always be truncated to 32 bit(for example m*x gives a 64 bit value which has to be truncated to 32 bit after the multiplication) . The final value should be in 4.28 format [i.e.,4 for integer part and 28 for decimal part(fractional part)] . In the integer part one bit will be for sign and there are left with 3 more bits which can have a maximum value till 7, and the decimal part consists of 28 bits ,so the value will be + or - 7.9 for 4.28 m and x should take decimal values

I need to use GitLab CI to check for students' work assignment (language VHDL (run with GHDL) if that matters). The idea is that I have a "secret" testbench, which is compiled with student's code (submitted as git commit to GitLab), and the job needs to check if the submission passes the test. There must be zero possibility for the student to misuse the GitLab to get access to the secret code. Preferably the secret code is stored and run in a separate computer (than gitlab-runner). Deliverables: - Description how the objectives are met - Installation instructions (if any) - Example project with CI pipeline - Source codes of customized scripts / code (C or C++ allowed). Please note: - GitLab CI allows to run arbitrary code in the CI-job, thus the student wi...

Campera Electronic Systems is planning to introduce a Verification methodology in the company verification flow for VHDL designs. Previous experience on one of the "standard" VHDL verification methodologies (UVVM, OSVVM) or framework (Vunit) is requied.

...a project in the labs during the 9th to 13th week of the semester. The practical demonstration will take place last week. Using BUT e-learning, students submit a link to the GitHub repository, which contains the project in Vivado, the necessary images, documents and a descriptive README file. The submission deadline is the day before the demonstration. The FPGA source codes must be written in VHDL and implementable on the Nexys A7-50T board in the development tools used in the laboratory during the semester. Make testbenches for all your new components. Physical implementation on FPGA is necessary, computer simulation is not sufficient. Never, ever use rising_edge or falling_edge to test edges of non-clock signals under any circumstances! In a synchronous process, the first...

I'm looking for an expert in VHDL and Quartus II from Pakistan to design a specific digital system of intermediate complexity. The ideal freelancer will have experience in designing digital systems using VHDL and Quartus II.

BCD multiplier development using Verilog HDL for Xilinx FPGA technology Input/Output Format: - Desired input/output format is Binary Testbench: - Testbench required for the Verilog code Ideal Skills and Experience: - Proficiency in Verilog HDL - Experience in BCD multiplier development - Expertise in Xilinx FPGA technology - Familiarity with Binary input/output format - Ability to create a testbench for Verilog code Goals: - Develop a functional BCD multiplier using Verilog HDL - Ensure the Verilog code passes the testbench - Optimize the design for Xilinx FPGA technology.

Ju lutemi Regjistrohuni ose Identifikohuni për të parë të dhënat.

Design a push-button door lock that uses a standard tele-phone keypad as input.

I need a code in VHDL for a custom IP to communicate with the DDR4 MIG, it can be through a DMA block with FIFO over the AXI bus. Everything must be done on the PL side, and must have the basic functions of writing and reading a data at a memory address. The code will be tested on the ZCU104.

This is a project where you will use a DE 10 Standard Board to detect audio data. It should detect snaps and under instructions, look at ideas in the instruction areas, there are highlighted other functions there. The files and everything else necessary to complete to complete the poject are in this google drive. Thank you.

using Artix 7 implement Master UFS protocol design for the UFS Host device, Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c) Skills required : Verilog , VHDL , C

I need a full verliog code that will output a "32-bit microprocessor using an FPGA board" 1. High level text description to describe HOW you are implementing your project. 2. DETAILED Block Diagram(s) showing design and detailed interconnections. 3. List of tasks completed 4. List of things I need to simulate, debug, and demonstrate 5. Data sheets for each IC used in your design. 6. Worst Case analysis - show tables / spread sheets in progress in process for Noise margin, Loading, Timing 7. I WILL NEED A VIDEO EXPLAINING HOW THE CODE WORKS (IN ENGLISH) 8. ALSO PICTURES OF THE CODE RUNNING SMOOTHLY NO PLAGIARISM PLEASE PLEASE COME UP WITH YOUR OWN CODE

printer coding vhdl coding zynq 7020

Embedded Linux with FPGA capability. From VHDL to application level programming.

We are Hiring Technical expert (Xilinx Vivado) Position: Academic Technical expert Freelancer Experience: 2+ years Qualification: Masters or Doctorate in Electronics & Communication Engineering Skills Required: Turbo Decoder VLSI Xilinx Vivado FPGA Verilog Machine learning Specific area: Need a Verilog, Xilinx Vivado and Machine learning expert Time: Part-time/Freelance Job Description: Require a Freelancer, who can do coding will be done on Xilinx Vivado. Implementation will be done on FPGA using Verilog/ system Verilog language

Looking for FPGA Developer who has experience in VHDL on SoC FPGA architecture