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    4,795 verilog vhdl punët e gjetura, me çmimin EUR
    16139 Praca z vhdl/verilog Ka përfunduar left

    Witam mam do napisania prace z języków opisu sprzętu. Temat: Opracowanie systemu mikroprocesorowego. Posiadam materiały i troszke mam napisane mogę to udostępnic. Zakres: przygotowanie modeli oraz wizualizacji wyników w VHPI, PLI.

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    Matlab Help Ka përfunduar left

    Take an RGB image and split it into 8*8 blocks in Matlab for me. Send me screenshot of the output.? You can read the image in matlab using imread command....then it will store in a variable...then by using csvwrite command you can write data into a file. And if you know how to use this ...split it into 8*8 blocks in Matlab for me. Send me screenshot of the output.? You can read the image in matlab using imread command....then it will store in a variable...then by using csvwrite command you can write data into a file. And if you know how to use this data as input in a DCT block in VHDL for JPEG Compression, please tell me otherwise just do the first part.? Need it fast. ## Deliverables Must be in Matlab or VHDL. I prefer VHDL but Matlab is good too. I'll pay hig...

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    i designed a datapath and now i need to simulate it with VHDL,but i dont enough time to learn it..just simulate it... ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows? (depending on the nature? of the deliverables): a)? For web sites or? other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software? installation package that will install the software in ready-to-run condition on th...

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    TOR3 Board Ka përfunduar left

    I need someone with experience in TOR3 boards () who can help me finish the open source PCI gerber and BOM. I also need help finding the VHDL to program the Xilinx chip.

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    Hi everyone, I have project, Division by repeated Multiplication, the project is implement the Division by repeated multiplication algorithm in VHDL (IN STRUCTURAL CODE, NOT JUST BEHAVIORAL CODE). since I was running out of time, if there's anyone out there has been mastering on this or ever did this kind of project please help me. I will be so very thankfull by this. really. looking forward to your helps... Thanks, Regards, Steve. PS. I need the final code including the testbench and the syntesis result on the general purpose fpga (in terms of area, delay and energy consumption)

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    Verilog to VHDL Conversion Ka përfunduar left

    Convert this verilog project to vhdl ## Deliverables Convert a verilog project to vhdl

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    • Design in VHDL • Convolution • Correlation • Filtering • Implementation on an FPGA board

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    VHDL programming Ka përfunduar left

    I am currently doing a project of which Im building a central heating prototype. this is done using FPGA spartan 3 starter kit. and I need help with programming it in VHDL. I have done all the hardware and includued everything in the file, all I need is the VHDL codes, for LCD interfacing, and programming a digital thermostat I used in my daughterboard and many other features you will find described in the file attached with this. Please have a look at my propsal and let me know if you can do it. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. ## Platform FPGA spartan 3 starter Kit.

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    need verilog code for:Ascii to hex convertion

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    ...generate/interface the following signals SE, SDI, SDIFS, SDOFS, SDO, MCLK, SCLK. This is a starndard SPORT interface (much like SPI) so few of you may even have this already implemented. So you must generate the clock (using clock divider, code can be provided on request) to supply the clock to the AD73360, write Verilog code to interface with the AD73360 so that it is able to receive data from the ADC. I want to able to write registers and get values in NIOS processor. Basically you will write Verilog (NOT VHDL) code to interface to the ADC and provide C functions/program that will run in the NIOS processor. Functions must be able to 1. Write all registers 2. Read all registers 3. Read values of all 6 channels and save them in 6 integers Sampling rate...

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    Please read the attachment the code requested is in the last two pages...

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    8 ofertat

    Please read the attachment the code requested is in the last two pages...

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    Please read the attachment the code requested is in the last two pages...

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    INTRODUCTION:? ? The project involves the implementation of the architecture of super scalar pipelined DLX (Delux) processor for the execution of certain instructions. The different instructions the processor would execute are:? ALU instructions:? ADD, SUB, AND, OR, XOR, SRA. We have signed, unsigned, and immediate type for ALU type instructions. I need for some types like ADDI, S...AND, OR, XOR, SRA. We have signed, unsigned, and immediate type for ALU type instructions. I need for some types like ADDI, SUBU. Etc. ? Branch Instructions:? BNEZ, BEQZ.? Load and store Instruction:? LH, SB, etc? Jump type Instructions: J, JAL. We have only four types in jump. Any two of them would be fine.? ? more info attached... ## Deliverables use xilinx software with verilo...

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    13687 Prosta gra w AHDL/VHDL Ka përfunduar left

    Zlecę napisanie prostej gry w AHDL lub gry podany po zaakceptoeaniu przez mnie oferty Założenia: -płytka ma sie komunikować z komputerem za pomocą portu USB, dostarczam moduły obsługujace te transmisję -stan autioamtu głównego ma być wyświetlany na wyswietlaczu LCD, dołączam moduł obsługujący.. Oferty,wraz z ceną proszę składać na portalu, z zainteresowanymi skontaktuję się osobiście

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    Ju lutemi Regjistrohuni ose Identifikohuni për të parë të dhënat.

    I vulosur

    "Automation of state reduction process of sequential circuits " is an engineering project. We have to write the code in VHDL language of any model like structural , behavioral or data flow methods. in this project, firstly we have to write a code how we reduce the states assuming approx 20 states and then including don't care states as well. after this , we have to implement this reduction on implication chart. we have to write a code for the implication chart as well to find out the final answer. I'm attaching some zip file ..you can go through them..ok ...you can view the process from pages 15 to 23..ok. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliver...

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    Altera DE2 coding in Quartus Ka përfunduar left

    This is a straightforward project for anyone familiar with using the Altera DE 2 development board and the Quartus software.? The project is to help code a system using the drah and drop NIOS processor, read a voltage input, display using the lcd screen and drive a stepper output.? ? Coders who are familiar with vhdl, quartus and the altera cyclone 2 will find this very straightforward.

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    I need to do Soundex Algorithm in VHDL language in Xilinx software. A simple name as the input for example my name 'NAUFAL' => then will be converted based on the soundex algorithm and table => and will give the output of 'N160'. I already make the research and I will provide all the details needed such as the description of soundex, flowchart, and etc. Hope to hear from you asap. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Del...

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    VHDL Code required Ka përfunduar left

    I have three questions related with VHDL. YOu have to write the complete State machine and then VHDL code for each problem in the tool called "XILINX". The questions are not difficult. Please read the attached file for the description of each question. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop s...

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    VHDL Ka përfunduar left

    2 questions to solve using VHDL, code must work properly though implementation is not important. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software installation package that will install the software in ready-to-run condition on the platform(s) specified i...

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    MPEG-2 video encoder project. I have the block diagram as well as the specifications. Need Verilog HDL coding for the encoder. Major blocks include Discrete cosine transform, Quantization, Run length encoding and Motion estimation. The input to the encoder is taken in YUV format from a camera source. A completed project would be paid $300. Deadline for this project is dec 25th, 2007. ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be insta...

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    Easy VHDL Filter System Ka përfunduar left

    Please see attached document for details VHDL Code and Testbed for System Required (Simulation Optional) Simple Arithmetic operations Needed ASAP (within 24Hours) Thanks in advance! ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software inst...

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    VHDL Syntax Guide Ka përfunduar left

    I'm in need of a detailed guide to VHDL syntax. You can use this as a guide but don't put in any examples, just syntax. I don't want you to copy this link exactly either, put it into your own words. Here's the link, and add what's missing to this link: <> ## Deliverables Rent A Coder requirements notice: As originally posted, this bid request does not have complete details. Should a dispute arise and this project go into arbitration "as is", the contract's vagueness might cause it to be interpreted against you, even though you were acting in good-faith. So for your protection, if you are interested in this project, please work-out and document the requirements onsite. 1) Complete and fully-functional working

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    hey I wanted the vhdl code for the following..... could you help me out with this..... --Design and synthesize a simple vending machine on the Spartan 3 or Spartan 3E board with the following features: --􀂾 The vending machine has four products. They cost 75, 80, 85, or 90, cents each. Use the slider switches (SW0 thro SW3) to select one of the products. --􀂾 Use two of the seven segment displays (or the LCD) to display the cost of the product entered --􀂾 Assume the vending machine only accepts $1 bills. Press BTN0 to pay for the product. --􀂾 Dispense the product by activating an appropriate solenoid (turn on an LED for 1 second to indicate the specific product is being dispensed) --􀂾 Using the other two seven segment displays show the change required

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    Hi all, We are looking for a Software engineer which will cooperate with my company's engineers and developers, in the development of a new product. In general, the product is an electronic device which acts as a voltmeter. The selected engineer will have to write the software part for the used hardware. The technical knowledge required is as follow: VHDL Language, Xilinx or Altera tools, Modelsim for simulation, Writing Test benches. The most important issues are the candidate's communication skills and loyalty. The company team includes employees from all over the world (India, USA, Israel, Macedonia..), and therefore professionalism, commitment and dedication are required. This is a very serious and multi modules project with tight deadlines. Workers of...

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    Delhi Public Ka përfunduar left

    Delhi public school problem ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's enviro...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement...

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    Hi all I'm having a trouble in chip design work. I want an program source code (in any programming language) that - Import any designs based on VHDL source code or netlist exported from Xilinx or Altera Development Tool (Quartus, ISE,...) - Parse and Implement any algorithm that will modify the design to give an new design which power consumpt is reduced - Certainly, output is the new power optimized netlist or VHDL source code that can be imported again to Quartus or ISE (xilinx). To prove that power consumption has been reduced in modified design, I will test base on power estimate tool of Quartus or ISE. Although these development tools have optimized power when synthesis but I want to do it myself. So you can use any algorthm that can optimize power such as RTL isola...

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    Ju lutemi Regjistrohuni ose Identifikohuni për të parë të dhënat.

    I have a design that needs verilog code written to act as a JTAG TAP Master. It gets commands and data from another chip and needs to output JTAG commands. This all needs to fit into a 64 macrocell CPLD. This project will be worked on together as I will provide logic traces and you will program the verilog so the jtag signal closely matches the logic traces. I wish for someone to be in Northamerica so the time-zones are close enough for real-time communications. Please send me a PM if you are interested and I will post the logic traces for you to examine. This project is VERY SIMPLE (how complex can you get with 64 macrocells =D)

    €93 - €278
    I vulosur
    €93 - €278
    4 ofertat

    A VHDL school project is required. The task is to designe and implement a microprocessor with 10 - 15 instructions and with the ability to add 3-4 more easily in the future. The instructions will be defined with / by the coder who will win the bid. These instructions are ADD, SUB, OR, AND, XOR, some instructions to compare data and jumps are required. You will need to define an architecture of microprocessor to accomplish these instructions (1, 2 or 3 buses) and to implement it in VHDL. For the design phase some drawings will be required to express the solution (e.g.: buses, registers, ...). For the implementation part comments are required so that I can easily understand how it works. Also, some support from your side after the project is finished will be highly apreciated i...

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    Implement a special efficient pipelined DDR-SDRAM controller into a Spartan 3 FPGA as described in the attached docuement ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software installation package that will install the software in ready-to-run condition on the platf...

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    VHDL project (Xlinx) Ka përfunduar left

    Urgent VHDL project till 10.06.2007!!! ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software installation package that will install the software in ready-to-run condition on the platform(s) specified in this bid request. 3) All deliverables will be considere...

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    Implement a special efficient pipelined DDR-SDRAM controller into a Spartan 3 FPGA - Pipeline (incl. bank switching) - Read a 64bit value - incremet and write back the 64 bit value to the same adress - during wait cycles on the one bank the...bank the same process should run on the other bank (alternating) - total 4 independant DDR-SDRAMs connected to the Spartan3 - SDRAM type: V58C2512164SAJ-5 - Spartan3: XC3S1500FG676 - speed: DDR SDRAM clock min 96 MHz, no "NOP" cycles in access - hardware already available We provide UCF-file and Verilog interfaces to our logic. If necessary we can provide an evaluation hardware. Expected deliverals: Xilinx ISE 9.1 project including well-documented Verilog sources and simulation We will check for pro...

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    We are in need of a simple C# GUI tool to generate and parse Verilog module hierarchies. The software must have the following capabilities: - Represent a Verilog design in an editable graphic format, like the schematic style of a regular electric/digital/UML schematic application. In the main window, it should be possible to add new modules (graph nodes), new signals (graph edges) and modify them as in any Windows GUI application (eg drag and drop, undo and redo, etc.). A secondary window should display the hierarchy in a graphical tree. The GUI must be designed in a C# tool like Microsoft Visual .NET (Express edition is ok). A design should be loaded and saved in an XML file. - Parse a group of Verilog code design files and extract the hierarchy of modules they contai...

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    VHDL(repost) Ka përfunduar left

    attached are the complete requirements ... ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ...

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    VHDL Ka përfunduar left

    attached are the complete requirements ... ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ...

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    HDL Ka përfunduar left

    Using Aldec’s Active-HDL Version 6.3 Student Edition design tool, develop a Verilog description and a schematic of the MINIMIZED COMBINATIONAL DIGITAL LOGIC FUNCTION BELOW: - Use K-MAP method to minimize the following boolean expression in S-o-P Form. F(A,B,C,D)= (ABC + !A!B) (C + D) ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all other...

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    Hi, I have 2 problems of asynchronous sequential circuit problems to be solved. I need these done as soon as possible. Attached are the problems in a doc file, thank you for bidding. please bid for all the problems, if you cant, bid according to how many prpblems u can solve. ## Deliverables 1) Complete and fully-functional working program(s) in...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform VHDL,...

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    VHDL Lab # 4 Ka përfunduar left

    Hi, please see the attached file. I need this lab to be done in VHDL code, also, i use xilinx 8.0 and 9.0 and you can download a free at xilinx web pack. need this done withn 1 day or so. but try to get as much as you can . thank you ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or soft...

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    Hi, I have 2 problems of asynchronous sequential circuit problems to be solved. I need these done as soon as possible. Attached are the problems in a doc file, thank you for bidding. please bid for all the problems, if you cant, bid according to how many prpblems u can solve. ## Deliverables 1) Complete and fully-functional working program(s) in...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform VHDL,...

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    VHDL Lab Project Ka përfunduar left

    See the attachement. In the attachment, Lab and MY4ALU are already done. Now, read the Lab 2. doc, i use xilinx 9.1i, and i need this done within 1-2 days without no errors. Previous coder did not do well, I have 3 more similar project and the winning coder will get more work. let me know if you have any questions. thank you ## Deliverables 1) Co...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform ...

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    VHDL lab Ka përfunduar left

    See the attachement. In the attachment, Lab and MY4ALU are already done. Now, read the Lab 2. doc, and i need this done within 10 - 15hrs or soon. thank you ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## P...

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    hi, i need help on a lab, attached is what to do, you should have experience with Xlinx ISE tool, its a 4 bit ALU design. should provide the output and benchwave form results. Need this within 10- 12 hrs from now. thank you more work will be given throughout this year. so more work from me to the coder. ## Deliverables 1) Complete and fully-functional working progr...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Pla...

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    Xlinx Project(repost) Ka përfunduar left

    hi, i need help on a lab, attached is what to do, you should have experience with Xlinx ISE tool, its a 4 bit ALU design. should provide the output and benchwave form results. Need this within 10- 12 hrs from now. thank you more work will be given throughout this year. so more work from me to the coder. ## Deliverables 1) Complete and fully-functional working progr...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Pla...

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    €28 - €93
    0 ofertat
    4 bit ALU, Xlinx Project Ka përfunduar left

    hi, i need help on a lab, attached is what to do, you should have experience with Xlinx ISE tool, its a 4 bit ALU design. should provide the output and benchwave form results. Need this within 10- 12 hrs from now. thank you more work will be given throughout this year. so more work from me to the coder. ## Deliverables 1) Complete and fully-functional working progr...on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Pla...

    PHP
    €11 (Avg Bid)
    €11 Oferta mesatare
    1 ofertat

    A VHDL school project is required. The task is to designe and implement a microprocessor with 10 - 15 instructions and with the ability to add 3-4 more easily in the future. The instructions will be defined with / by the coder who will win the bid. These instructions are ADD, SUB, OR, AND, XOR, some instructions to compare data and jumps are required. You will need to define an architecture of microprocessor to accomplish these instructions (1, 2 or 3 buses) and to implement it in VHDL. For the design phase some drawings will be required to express the solution (e.g.: buses, registers, ...). For the implementation part comments are required so that I can easily understand how it works. Also, some support from your side after the project is finished will be highly apreciated i...

    €105 (Avg Bid)
    €105 Oferta mesatare
    13 ofertat

    I need a expert in VHDL/Verilog behavioral. If you are please PM me, for more info on the project. Thank you

    €28 - €93
    I vulosur
    €28 - €93
    0 ofertat