Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers. Punësoni Verilog / VHDL Designers

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    I need help programming a microcontroller (PIC16LF1902-I/SS). The micros job is to count the duration of a momentary switch being activated, and compare that time to the stored highest time previously reached on that device. The output screen is a GDC0209 ( , ) The switch is a vibration sensor. I need to current draw to be 400uA when the device is running and displaying the time. Attached is the functional requirements. Please ask me whatever questions you have

    €339 (Avg Bid)
    €339 Oferta mesatare
    17 ofertat
    monitoring of Zynq Ultrascale + 6 ditë left
    VERIFIKUAR

    Using Vitis + Vivado build a software routine to monitor the execution of software on a heterogeneous platform (Zynq Ultrascale +). The monitoring systems are already built inside the hardware platform and will be opportunely controlled by the developed software routines that we want to build.

    €176 (Avg Bid)
    €176 Oferta mesatare
    3 ofertat

    Need help with improving an existing system verilog code. Reach out to me if you have experience with system verilog code.

    €186 (Avg Bid)
    €186 Oferta mesatare
    9 ofertat
    €6 - €19
    3 ofertat

    Two 16-bit number from X0 and X9 and H0 to H9 multiply them and add them . Code shall be done in VHDL Y= x0h0+x1h1+x2h2+x3h3+........x9h9. For more details find the attached Set of Question.

    €100 (Avg Bid)
    €100 Oferta mesatare
    4 ofertat
    orCAD Software Expert 5 ditë left
    VERIFIKUAR

    Task1: An audio signal processor has to attenuate a specific range of frequencies in the specified stop band and allowing the frequencies to pass outside the stop band. Design a prototype 4th order active band stop filter and 6th order active band stop filter using Butterworth filter for a desirable resonant frequency and bandwidth as per the given block diagram representation. Task2: In a combinational logic circuit the decoded output depends on the specified combination of bits at the data input. 1) The simulation design should be done for the combinational logic circuit such that it has three input lines and eight output lines. 2) Develop a truth table and the logic symbol for the combinational logic circuit designed.

    €28 (Avg Bid)
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    1 ofertat
    Circuit design 4 ditë left

    Need a circuit integrating multiple simple circuits

    €320 (Avg Bid)
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    17 ofertat

    The project is to design a system with an FIR filter for voice filtering in real-time. The work will be on Xilinx and Modelsim to design the system and also with Matlab so it's a big project and require time. It's a big project but the budget is average so please don't bid me high.

    €506 (Avg Bid)
    €506 Oferta mesatare
    12 ofertat

    The project is to design a system with an FIR filter for voice filtering in real-time. The work will be on Xilinx and Modelsim to design the system and also with Matlab so it's a big project and require time. It's a big project but the budget is average so please don't bid me high.

    €185 (Avg Bid)
    €185 Oferta mesatare
    3 ofertat

    To whom it may concern, I'm looking for someone experienced who can develop a basic calculator using verilog on vivado with specific requirements in a short period of time. If you think this fits your skills, let me know and lets discuss things further!

    €22 (Avg Bid)
    €22 Oferta mesatare
    7 ofertat
    Verilog on a weekend :) 4 ditë left
    VERIFIKUAR

    Hi, I have a couple of Verilog questions and would be happy to pay to pick someones brain! Attached is a simple HLS program that I synthesized to Verilog. I have some experience writing very basic Verilog programs, but some of the stuff would need an explanation. Attached is the Verilog project. And below in the text you will find the original HLS snippet. Ideally we would walk through the code an load the Verilog into Vivado and play a bit around with it for 2-3 hours while I ask a couple of questions. (1) CORDIC method is it applied here? (2) How does the entire program work? Honest question. (3) Why is there so much paramter overhead etc? (4) How would you simplify the application in Verilog? Requirements === (1) Happy to grab a Zoom or phone call (asked support seems to be okay) (2...

    €41 / hr (Avg Bid)
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    6 ofertat
    Dc motor pwm , vhdl using fpga 4 ditë left
    VERIFIKUAR

    I want code and testbench for Dc motor pwm by vhdl and using fpga Model of fpga kit ( DE10-Lite)

    €29 (Avg Bid)
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    4 ofertat

    you will be implementing a pipelined MIPS processor datapath with the following features: 1) FDEMW 5-stage pipeline with branch

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    3 ofertat
    FPGA Project 3 ditë left

    1 Verilog/VHDL Programming language 2 Understanding of the protocol and standards 3 FPGA knowledge & Programming hands on 4 Knowledge of the safety standards. Optical Data link 5 Networking concepts

    €352 (Avg Bid)
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    10 ofertat

    Need help designing an adder architecture in Verilog/Systemverilog.

    €20 (Avg Bid)
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    7 ofertat

    you will be implementing a pipelined MIPS processor datapath with the following features: 1) FDEMW 5-stage pipeline with branch

    €18 (Avg Bid)
    €18 Oferta mesatare
    1 ofertat
    Image Equalizer 1 ditë left

    I need an image equalizer written in VHDL language. The semplified algorithm to use should be: DELTA_VALUE = MAX_PIXEL_VALUE – MIN_PIXEL_VALUE SHIFT_LEVEL = (8 – FLOOR(LOG2(DELTA_VALUE +1))) TEMP_PIXEL = (CURRENT_PIXEL_VALUE - MIN_PIXEL_VALUE) << SHIFT_LEVEL NEW_PIXEL_VALUE = MIN( 255 , TEMP_PIXEL) In this project the program recieve the image dimension in 2 bytes, the first one is for columns and the second one is for rows. The third byte is the first byte of the image that the program recieves in input. Extra Notes: 1. FLOOR(LOG2(DELTA_VALUE +1)) is an integer number 2. The project should be able to process more than one image, but the input image will never change during the execution, only when the DONE signal is high 3. The module will start processing when the S...

    €181 (Avg Bid)
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    7 ofertat

    I am using a 32x32 LED matrix from Adafruit and I am driving it with an FPGA. I followed the tutorial they provided and I get an image initialize. Now, I am trying to have various frames to show, to make some sort of video. I want to use a microcontroller to send the data for the frames to the FPGA. Further explanation is attached on the word document and all the files I currently am using will also be attached. Please don't hesitate to reach out with any questions regarding the design.

    €619 (Avg Bid)
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    17 ofertat
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    11 ofertat
    Ac voltage measurement circuit 20 orё left
    VERIFIKUAR

    ac voltage measurement circuit and output of this circuit is in adc and send to pic16f877a

    €33 (Avg Bid)
    €33 Oferta mesatare
    11 ofertat

    Design 4 bits arithmetic unit that add, multiply and subtract using PTL & Domino *****simulate using cadence***** The app takes 3 inputs A, B, and C A, and B are 4 bits operands C is a 2 bits number (input for a multiplexing circuit) representing the operation Deliverables: 1- a step by step word file of the work done 2- all cadence files

    €29 (Avg Bid)
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    3 ofertat

    I need someone who can develop a current small project written in VHDL. It should be a game dispaying on vga monitor.

    €64 (Avg Bid)
    €64 Oferta mesatare
    6 ofertat

    To design and implement a robotic system, NIOS2 processors are considered vital as they provide security and reliability. You are required to program and demonstrate a 16-bit NIOS2 processor for the given instruction set in VHDL. You are required to design and implement each component such as arithmetic logic unit (ALU), memory system, control unit etc. separately in VHDL and verify them on FPGA board. Moreover, you are required to integrate all these components in VHDL and demonstrate the complete system design on the FPGA board

    €9 - €16 / hr
    I vulosur
    €9 - €16 / hr
    1 ofertat

    To design and implement a robotic system, NIOS2 processors are considered vital as they provide security and reliability. You are required to program and demonstrate a 16-bit NIOS2 processor for the given instruction set in VHDL. You are required to design and implement each component such as arithmetic logic unit (ALU), memory system, control unit etc. separately in VHDL and verify them on FPGA board. Moreover, you are required to integrate all these components in VHDL and demonstrate the complete system design on the FPGA board

    €19 - €159
    I vulosur
    €19 - €159
    2 ofertat