Verilog / VHDL Punë dhe Konkurse
Verilog is a description language used in the field of semiconductor and electronic design. It is also used in analog and mixed-signal circuits. VHDL is a hardware description language used in electronic design automation and integrated circuits. If your business is working with Verilog / VHDL then you can use some freelancer help to ease the workload. Post your Verilog/VHDL job today to connect with such freelancers.
Kërkoni Punë në Freelancer
| Projekt/Konkurs | Përshkrimi | Oferta/Propozime | Aftësi | Filloi | Përfundon | Çmimi (EUR) | |
|---|---|---|---|---|---|---|---|
| build a very simple MIPS code | I need a simple MIPS code. I will send you the task. I need it in an hour. | 5 | Programim C, Java, Verilog / VHDL, Programim në gjuhën C++ , Programim në gjuhën Assembly | Apr 22, 2018 | Sot6d 20o | €15 | |
| FPGA Design and Asic | Hi there Please check the document | 7 | Inxhinieri, Elektronikë, Verilog / VHDL, Inxhinieri Elektrike, FPGA | Apr 21, 2018 | Apr 21, 20185d 19o | €28 | |
| FPGA Design | Hi there Please check the document! | 6 | Inxhinieri, Elektronikë, Verilog / VHDL, Inxhinieri Elektrike, FPGA | Apr 21, 2018 | Apr 21, 20185d 19o | €12362 | |
| Floating Point on DSP48E1 | I need to implement floating point single precision algorithm (add,sub,mul,div)(standar IEEE754) on unit DSP48E1. I need a File Register on 48bit, a priority encoder on 32b, an exponent unit where is stock the sign and exponent and a sequencer(Delay Mealy automata) who give the comand to DSP. Can anybody help me? Thank you! | 5 | Verilog / VHDL, FPGA | Apr 21, 2018 | Apr 21, 20185d 15o | €199 | |
| MIPS Computer Design by Verilog HDL | I have Computer engineering project to design Single Core ad Single Bus CPU, to built in Verilog HDL | 16 | Inxhinieri, Verilog / VHDL, Programim në gjuhën Assembly, Projektim dixhital, FPGA | Apr 20, 2018 | Apr 20, 20184d 19o | €109 | |
| need to implement an ieee paper using verilog or vhdl. -- 2 | would like to get the implementation of given ieee paper using verilog/vhdl within 15 days | 4 | Verilog / VHDL | Apr 20, 2018 | Apr 20, 20184d 16o | €101 | |
| 200418_Verilog | All code is written/run on the Quartus Prime version 16 environment =========================================== You have to know Verilog. Please bid only if you know Verilog perfectly Deadline: 72 hours | 4 | Elektronikë, Verilog / VHDL, Inxhinieri Elektrike | Apr 20, 2018 | Apr 20, 20184d 14o | - | |
| Conceive SDR GnuRadio blocs | This project aims at conceiving GNU-Radio blocs for receiving / transmitting modulated radio messages using Software Defined Radio (SDR). I need a software component lib called "gr-beaglesdr" of a software-defined radio receiver and transmitter combined with suitable hardware device BeagleSDR. It can be used to listen to or display data from a variety of radio transmissions and also send... | 4 | Linux, Elektronikë, Verilog / VHDL, Mikrokontrollor, Inxhinieri Elektrike | Apr 20, 2018 | Apr 20, 20184d 10o | €569 | |
| Implementing Bit stuffing in verilog | Bit stuffing is the process of inserting non-information bits into data to break up bit patterns to affect the synchronous transmission of information. For a serial sequence 10111110; a stuff bit '0' should be added after every 5 consecutive 1's and vice versa when there are consecutive 0's | 9 | Inxhinieri, Verilog / VHDL, Mikrokontrollor, Inxhinieri Elektrike, FPGA | Apr 20, 2018 | Apr 20, 20184d 6o | €25 | |
| Edge detection by using laplacian | I want a freelancer for making a project who have strong knowledge of mpi and Openmp c++.If any one interested let me know so we can discuss it further Your task is to implement an initial serial version of the program, where it takes an image as an input and then produces an output image after applying the stencil matrix(Laplacian ) on the input image. Then, you should try to optimize the co... | 1 | Programim C, Verilog / VHDL, Arkitekturë Softuerësh, CUDA, Programim në gjuhën C++ | Apr 19, 2018 | Apr 19, 20184d | €121 | |
| Sending and receiving tcpip xgmii packets over SFP+ | This is an FPGA/Verilog project to send some TCP packets over 10g SFP+ network to a tcp server. | 4 | Verilog / VHDL, FPGA | Apr 19, 2018 | Apr 19, 20183d 17o | €379 | |
| plc program and hmi design Simulation | I have Program pLc program and Hmi design for academics project just to simulating the code with software need basic help | 13 | Inxhinieri, Elektronikë, Verilog / VHDL, Mikrokontrollor, Inxhinieri Elektrike | Apr 19, 2018 | Apr 19, 20183d 14o | €16 | |
| develop Simple SW to write on the IC Card/Server | I have IC cards or integrated chip cards that i needed to write on them. So, i am looking for simple SW and support for successful testing of this beta version design. My design and solution is almost the same as access control however it has its own different use cases. So, let’s assume that I need to create SW solution for access control within a hotel or company using IC card i... | 4 | Programim C, Elektronikë, Verilog / VHDL, Mikrokontrollor, Faqosje PCB | Apr 19, 2018 | Apr 19, 20183d 11o | €231 | |
| translate C++ code in systemc. | translate c++ code in systemc and implement constrained random verification methodology. | 5 | Programim C, Verilog / VHDL, Arkitekturë Softuerësh, Programim në gjuhën C++ , Very-large-scale integration (VLSI) | Apr 19, 2018 | Apr 19, 20183d 11o | €23 | |
| build a software | translate c++ code in systemc. and implement constrained random varification methodology. | 2 | Verilog / VHDL, Arkitekturë Softuerësh, Programim në gjuhën C++ , Very-large-scale integration (VLSI) | Apr 19, 2018 | Apr 19, 20183d 10o | €35 | |
| Create a DLX Data Path Using VHDL | Looking for an experienced person that understands computer architecture and VHDL language to complete this task. The project will require you to create simulation files of each task that's asked in the attached document to verify it works properly. The code needs to be neat and commented in a way that explains what is happening in the code. | 8 | Verilog / VHDL, Mikrokontrollor, Arkitekturë Softuerësh, Programim në gjuhën Assembly, FPGA | Apr 18, 2018 | Apr 18, 20183d 2o | €145 | |
| build a software | translate a C++ code in systemc module. | 3 | Programim C, Verilog / VHDL, Programim në gjuhën C++ | Apr 18, 2018 | Apr 18, 20182d 22o | €25 | |
| convert the C++ language code in systemc. | you have to translate C++ code in systemc language. | 3 | Programim C, Verilog / VHDL, Arkitekturë Softuerësh, Programim në gjuhën C++ | Apr 18, 2018 | Apr 18, 20182d 20o | €27 | |
| Do VHDL project on the ModelSim | I want to do a VHDL project on ModelSim, all what you need will be in the attached document, i will need a report for the whole project ( explaining every file in the project and what it does ). I want phase 1 ( Design ) ASAP and the rest of the project within a week ( Maximum 10 days ). Please read the document carefully and if you have any questions contact me. Specify your price and time requir... | 11 | Inxhinieri, Elektronikë, Verilog / VHDL, Inxhinieri Elektrike, FPGA | Apr 18, 2018 | Apr 18, 20182d 15o | €125 | |
| SoundLocator | Android development of app client to send (internet) sound and inertial sampling Hardware design of server (FPGA/SoC) to compute RT responses of precise positioning and navigation, taking into account multipath, doppler effect by movement, .. Also desiderable "roaming" to GPS coordinates to map position | 14 | Java, Elektronikë, Android, Verilog / VHDL, FPGA | Apr 18, 2018 | Apr 18, 20182d 12o | €504 | |
| Serializer & Desrializer Implementation using ZC706 and MTX | Serializer & Desrializer Implementation using ZC706 and MTX | 6 | Verilog / VHDL, FPGA | Apr 17, 2018 | Apr 17, 20182d 4o | €24 | |
| OpenCL FPGA Code modification | I am looking for someone to modify the OpenCL code base of an AMD focused Crypto Mining Software and optimize it for OpenCL Based FPGA using this package [url u hoq, identifikohuni për t'a parë] Please respond directly with any questions such as specific mining software and such. | 7 | Programim C, Verilog / VHDL, Kriptografi, OpenCL, FPGA | Apr 17, 2018 | Apr 17, 20181d 23o | €1860 | |
| Circuit at logism | implement a digital circuit in Logisim for a door lock. | 3 | Elektronikë, Verilog / VHDL, Mikrokontrollor, Inxhinieri Elektrike, Projektim qarku | Apr 17, 2018 | Apr 17, 20181d 19o | €20 | |
| expert in vivado vhdl needed | expert in vivado and vhdl needed asap | 8 | Inxhinieri, Verilog / VHDL, Mikrokontrollor, Inxhinieri Elektrike, FPGA | Apr 17, 2018 | Apr 17, 20181d 16o | €20 | |
| digital logic design circuit in logisim | there should be A and B inputs and the circuit should check if the A is divisible by B or not. and division should be worked like 10-2=8-2=6-2=4-2=2-2=0 then 10(a)is divisible by 2(b). we have only 30 minutes to do. | 9 | Inxhinieri, Elektronikë, Verilog / VHDL, Inxhinieri Elektrike, Projektim qarku | Apr 17, 2018 | Apr 17, 20181d 14o | €91 | |
| digital circuit in logisim | we should draw a circuit in logisim. there should be 2 input like A and B. the circuit should check if A is dibisible by B or not. you should work with ALU. and division should be worked like 10-2=8-2=6-2=4-2=2-2=0 then 10(a)is divisible by 2(b) | 6 | Elektronikë, Verilog / VHDL, Mikrokontrollor, Inxhinieri Elektrike, Projektim qarku | Apr 17, 2018 | Apr 17, 20181d 14o | €17 | |
| Signal Peak Detector, Digital Design - Command Processor | I am currently working on peak detector using VHDL entry (Modelsim and Xilinx), to design logic design in FPGAs to fulfill my free time. There are two parts, which are command processor and data processor. However, I have completed the data processor part, so only command processor left and I have no idea how to complete it. I plan to accomplish this task by next Sunday, 22nd April before I starte... | 7 | Inxhinieri, Elektronikë, Matlab dhe Mathematica, Verilog / VHDL, Inxhinieri Elektrike | Apr 17, 2018 | Apr 17, 20181d 14o | €37 | |
| Circuit in Logism | Given two 4-bit integers, A and B, build a circuit that can outputs 1 if A is divisible by B, or 0 otherwise. It should be done using 4 bit ALU | 8 | Inxhinieri, Elektronikë, Verilog / VHDL, Inxhinieri Elektrike, Projektim qarku | Apr 17, 2018 | Apr 17, 20181d 12o | €53 | |
| Logisim Digital Logic Design | using four bit ALU, given two numbers A and B we need to find if A is divisible by B | 15 | Inxhinieri, Elektronikë, Verilog / VHDL, Inxhinieri Elektrike, FPGA | Apr 17, 2018 | Apr 17, 20181d 11o | €64 | |
| Neural Network on an FPGA | I want to get a simple 3 layer (Input-Hidden-Output) layer neural network implemented on an FPGA. The network I wish to implement is a wide network with hidden neurons ~1000-2000. I want this to be implemented for highest data throughput with optimized resource utilization. Also want to software to be written for the implemented hardware. | 5 | Programim C, Verilog / VHDL, Mësim automatik (Machine Learning), FPGA, Neural Networks | Apr 17, 2018 | Apr 17, 20181d 6o | €129 | |
| CRYPTO MINING using VHDL in FPGA | Details later.. I will check your BASIC.. And then recruit You | 2 | Verilog / VHDL, Inxhinieri e minierave, Projektim dixhital, FPGA | Apr 15, 2018 | Apr 15, 2018Ka përfunduar | €1696 | |
| programming mplab | programm an fm receiver chip to be able a radio to work mp lab software using c or c++ everything exxplained in files that will be sent | 18 | Programim C, Verilog / VHDL, Mikrokontrollor, Programim në gjuhën C++ , Arduino | Apr 13, 2018 | Apr 13, 2018Ka përfunduar | €176 | |
| Experts on Communication system, Digital Signal Processing, and Matlab needed 2 - 12/04/2018 18:48 EDT | Like mentioned above, I have many task on this. I need experts in this field who can help. I do not want someone who cannot work at a reduced rate since order is regular. Only people who is experienced in this field should bid. Thanks | 6 | Inxhinieri, Matlab dhe Mathematica, Verilog / VHDL, Inxhinieri Elektrike, Inxhinieri Telekomunikacioni | Apr 12, 2018 | Apr 12, 2018Ka përfunduar | €25 | |
| Experts on Communication system, Digital Signal Processing, and Matlab needed | Like mentioned above, I have many task on this. I need experts in this field who can help. I do not want someone who cannot work at a reduced rate since order is regular. Only people who is experienced in this field should bid. Thanks | 3 | Inxhinieri, Matlab dhe Mathematica, Verilog / VHDL, Inxhinieri Elektrike, Inxhinieri Telekomunikacioni | Apr 12, 2018 | Apr 12, 2018Ka përfunduar | €16 | |
| Mips, Verilog project | Small project on computer architecture | 20 | Verilog / VHDL | Apr 9, 2018 | Apr 9, 2018Ka përfunduar | €17 | |
| State Machine and Timing Diagram for Embedded System | State Machine and Timing Diagram for Embedded System. More details to be provided. | 17 | Verilog / VHDL, Embedded Software | Apr 9, 2018 | Apr 9, 2018Ka përfunduar | €37 | |
| OS work ( Printing Service) | In this work, I need a coder who will design a programming solution to a variant of the boundedbuffer producer/multi-consumer problem using semaphores. The main goal of the task is to get familiar with the basic concepts of InterProcess Communication (IPC) and threads. Your implementation will be based on the following: shared memory, locks, semaphores and threads. More details will be prov... | 8 | Programim C, Java, Verilog / VHDL, Programim në gjuhën C++ , Programim | Apr 8, 2018 | Apr 8, 2018Ka përfunduar | €26 | |
| Systemverilog TCPIP model | Looking for a SystermVerilog TCPIP model which drives the MAC data to TCPIP DUT and analyze the data from DUT. Need some customization depending on the RTL. | 3 | Verilog / VHDL | Apr 6, 2018 | Apr 6, 2018Ka përfunduar | €151 | |
| NS3 simulation using c++ and ubunto NS3 simulator | NS3 simulation using c++ and ubunto NS3 simulator | 5 | Programim C, Linux, Verilog / VHDL, Arkitekturë Softuerësh, Programim në gjuhën C++ | Apr 6, 2018 | Apr 6, 2018Ka përfunduar | €296 | |
| ns3 project c++ ubunto needed | i need this simulation for ns3 using c++ | 4 | Programim C, Linux, Verilog / VHDL, Arkitekturë Softuerësh, Programim në gjuhën C++ | Apr 6, 2018 | Apr 6, 2018Ka përfunduar | €191 | |
| Simple SCADA WEB page | Web Page for monitoring data of sensor Login Security Historical reports Mobile COmpatibility Good Desing If you are interested you should write me a message saying you have experience in labview | 9 | PHP, Inxhinieri, Verilog / VHDL, Arkitekturë Softuerësh, LabVIEW | Apr 6, 2018 | Apr 6, 2018Ka përfunduar | €147 | |
| Vhdl coding for a small project | 1. Do some for loop in vhdl 2. Do some multiplication in vhdl 3. Add registers at input and output | 4 | Verilog / VHDL | Apr 4, 2018 | Apr 4, 2018Ka përfunduar | €26 | |
| Serial Interface using Python | Design a serial interface using Python for communication with FPGA. | 5 | Python, Verilog / VHDL, Ndërfaqe përdoruesi / IA, Arkitekturë Softuerësh, FPGA | Apr 2, 2018 | Apr 2, 2018Ka përfunduar | €26 | |
| Project for Usama S. | Hi Usama S., I noticed your profile and would like to offer you my project. We can discuss any details over chat. | 7 | Elektronikë, Verilog / VHDL, Hartim Kёrkimi, LabVIEW, , Shkrim Akademik | Apr 2, 2018 | Apr 2, 2018Ka përfunduar | €28 | |
| FPGA Programming Crypto Miner | I am looking for someone that can program or port an existing Windows or Linux mining program for AMD GPU's to a Xilinx Kintex-7 FPGA I will provide details and Github privately | 9 | Programim C, Elektronikë, Verilog / VHDL, Mikrokontrollor, Inxhinieri Elektrike | Mar 30, 2018 | Mar 30, 2018Ka përfunduar | €1160 | |
| parallel multiply simulation -vhdl | I need to create and minimize 2 small VHDL entities and their corresponding architectures. Can anyone help? I will provide with some files that are the basics to this, but still need to create 2 more. You need to be expert in VHDL language and have knowledge of computer architecture. | 13 | Programim C, Inxhinieri, Verilog / VHDL, Mikrokontrollor, FPGA | Mar 29, 2018 | Mar 29, 2018Ka përfunduar | €27 | |
| Implementation of Leach protocol on tinyos | I have a Wireless sensor network project, I need to implement the leach protocol on a hardware that is compatible with tinyos. You must have: -Theorical background on WSN. -Experience on implementation on Tinyos. | 1 | Programim C, Wireless, Inxhinieri, Verilog / VHDL, Programim në gjuhën C++ | Mar 29, 2018 | Mar 29, 2018Ka përfunduar | €15 | |
| JESD204B ADS54J20 vc707. - open to bidding | I have a project where i need to receive ads54j20 data with interface jesd204b on vc707. if your are interested please let me know and we can discuss details in a chat. | 6 | Elektronikë, Matlab dhe Mathematica, Verilog / VHDL, Mikrokontrollor, FPGA | Mar 28, 2018 | Mar 28, 2018Ka përfunduar | €587 | |
| Build me iv.file | I have a project that deal with LABView app, or as it called iv. file. I need someone who is good at creating scheme and using LABView | 7 | Verilog / VHDL, Mikrokontrollor, Arkitekturë Softuerësh, LabVIEW, Arduino | Mar 28, 2018 | Mar 28, 2018Ka përfunduar | €24 | |
| Implementation of Leach protocol on tinyos | I have a Wireless sensor network project, I need to implement the leach protocol on a hardware that is compatible with tinyos. You must have: -Theorical background on WSN. -Experience on implementation on Tinyos. | 3 | Programim C, Wireless, Inxhinieri, Verilog / VHDL, Programim në gjuhën C++ | Mar 28, 2018 | Mar 28, 2018Ka përfunduar | €49 |
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