technical content writer for the verilog, system verilog,uvm and ovm with project examples

Hi, I am a highly-skilled FPGA engineer with 6+ years experience and hundreds of FPGA/Verilog/VHDL projects using Xilinx/Altera FPGA Design Tools and Digital Logic Design using LogiSim/CEDAR. An FPGA/Verilog/VHDL Codementor and Founder of FPGA4student. Kindly contact me for further discussion. Thanks, Loi

Hello! I am a graduate in Electronics and Instrumentation Engineering from BITS Pilani Goa Campus, and am currently working as a freelance CPU Design Engineer. I am enthusiastic about Computer Architecture, Processor Micro-architecture, Digital design and allied fields. Over the years, I have gained skills essential to both Digital design and verification field including, but not limited to Universal Verification Methodology (UVM), Verilog for Synthesis, RTL-debugging and Processor designing. Given my background, I think I should be able to help you out on this project.

I have reviewed your bid request and I am very interested in your project. I was trained overseas and have an extensive customer service record so contact me so we can discuss further or begin. Relevant Skills and Experience Tech writing

Hi, I have 5 years experience in the digital design field please contact me for more details, Regards, Mohamed

Hi, I hope you are doing well and enjoying digital design. I believe implementing a design right form modeling until verifying it on an FPGA is always a very special experience. Throughout my 3+ years of experience in the field, I had the joy of designing and implementing a part of LTE's physical layer right from the Matlab model, through RTL coding, simulations, and back-end stages. I also built many other designs such as a MIPS processor design, Can satellite, and a UART transmitter and receiver. All my designs were verified successfully on either Xilinx's Spartan S6, S3, or Altera's Cyclone V FPGA. (You can refer to my portfolio) The project sounds really challenging which makes it much more appealing. I would love to hear your thoughts and requirements for the delivery as well. I wish you get the best out of this project. - Eslam

Master in Engineering, Electrical and Electronic Engineer, who is dynamic, reliable, resourceful, committed and organized with enthusiastic approach to succeed with a pleasant attitude. Possessing excellent analytical skill and good research background. I have successfully completed IELTS with an overall band of 7 and have a good proficiency in English COMPLETED PROJECTS • FM radio. • VHDL Design of an Up/Down Counter. • Design of Up/Down Counter using PIC. • Duck Shooter Program using C. • Pointer movement controller on 2-dimentional axis using C. • LCD display Manipulation projects including: o Text Display o Volt-Meter • Analog to Digital Conversion (8-bit). • Sound to Light Color Organ Design and Development. • Minesweeper Player Creation using PIC. • Simulation of an End to End Communication System with MATLAB. • (BENG Individual Project) (MENG Part A). • (MENG Individual Project) (MENG Part B). • (MENG Group Project).

I am working in the ASIC industry. I have been working in Cadence for two years. The project is definitely in areas of my expertise. I am very familiar with Verilog, Systemverilog, ovm and uvm. This is my first bid in Freelancer. Please consider me. I value this chance a lot.

I done many projects documents with DO 254 standard