VHDL code for Pipe lined MIPS-RISC (5 stage) processor.(Code for Un-pipelined will be given)
$30-250 USD
Mbyllur
Postuar over 6 years ago
$30-250 USD
Paguhet në dorëzim
I need you to do pipelining for the MIPS-RISC (5 stage) Processor. I will give you the MIPS processor code, all you need to do is pipelining. I will upload the file once go through it. If you are interested, I will send you the code and question for which code has written.”
Deadline is " Dec-03-2017 "
I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG.
Stay tuned, I'm still working on this proposal.
I have extensive knowledge on VHDL and digital design. I have experience with cpu architectures too. I will be more than happy to help.
Relevant Skills and Experience
VHDL
Digital Design
Computer architecture
Proposed Milestones
$200 USD - Delivery of pipelined MIPS RISC
Hey I am an expert in the field of RTL based development. I have done several projects using VHDL. I am also an expert in the field of computer architecture and have good knowledge of mips assembly. I already have a few working modules for mips assembly in vhdl and verilog. Please ping me up so that we could get this done asap.
According to JOB
Relevant Skills and Experience
I have implemented approximations 4000 m for various measurements from Pipes in several projects
Proposed Milestones
$75 USD - start
$80 USD - finish
I can show you many Pictures for these jobs