cache simulator

Design a generic cache module that can be used at any level in a memory hierarchy. For example, this cache module can be “instantiated” as an L1 cache, an L2 cache, an L3 cache, and so on,3 replacement policies to be used LRU,FIFO and optimal .Should be able to use Inclusive,non-inclusive and exclusive [login to view URL] give number of reads,writes etc for both as an output.