SERDES RTL DESIGN

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Also, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Aslo, I have experience in coding Booth multiplier and very familiar with Xilinx tools like ISE. and Vivado. Therefore, I can simulation the projecthe in behavior, post-syntheize... with free hesitation. I am also have experience of freelancer here: https://www.freelancer.com/u/ducdctoandh.html Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.

I am Senior Electronic Engineer with advanced knowledge of digital signal processing, and experience in the design of embedded systems in real time implemented with DSP, FPGA and Microcontrollers. In my experience in the aerospace area, I worked in high-speed designs on FPGAs using VHDL: - Core (ProASIC3 Microsemi): TM/TC data interface from/to a SAOCOM satellite's S-band transponder. The design included the logic of communication control, FIFOs, coding and data conditioning. - Core (FPGA Virtex5 Xilinx): payload data interface to two X-band SAOCOM satellite's transmitters. The design included the logic of communication control with a PCI Express IP Core, FIFOs, coding and data conditioning. In both designs the verification was carried out at the RTL level and "Post Place and Route" after the synthesis. In addition to performing the tests in the laboratory. I love working on complex designs, it motivates and excites me. I have the ability to solve problems, fast compression of what is required, and responsibility to carry out the work in the best way. I am new using the freelance platform, but sure that I am the person who can help you.   Best regards

Hello, I see that you’re looking for an experienced SerDes engineer to include SerDes block into ASIC, and would like to offer our team to get this done efficiently and in reasonable time. We are a team of electrical engineers/FPGA developers who have a broad experience with SerDes blocks; ASIC; Xilinx, Altera, Microsemi FPGA chips; VHDL and Verilog hardware description languages. In the scope of our projects we used integrated programmable ARM-based processor IP cores (Cortex-A9) and soft processor IP cores such as MicroBlaze (Xilinx), PicoBlaze (Xilinx), Nios II processor (Altera). We also worked with such interfaces and controllers as: SPI, UART, I2C; DSP system; FiFo controller, DMA controller, SD/MMC; SDRAM, DDR, DDR2 memory controllers. We understand what you need to get done and are ready to implement all the tasks required (writing PCS RTL code, providing you with a GTH transceiver configuration/RTL, as well as guidance on link channel verification). Will be glad to get in touch with you and discuss everything in person. I am sure we can be a god fit here and provide you with the required deliverables efficiently. Looking forward to working with you! Regards, Daniel

I am an experienced digital design engineer. I have designed LVDS and HDMI links before for video transmission onn spartan6-virtex5-kintex and zynq devices. Drop a line over chat if you have any questions. best regards, p.s. I can visit your office if turned to a longer term project.

I have successfully done communication using GTX, and I have exposure to GTH also. I have knowledge of PMA + PCS. I can do your project.

Hi, i am an experience hardware designer in Silicon Valley. Have designed hardware for high speed Serdes using 8b/10b encoding and PCS layer PHY used in data center applications. Familiar with both VHDL and Verilog, different coding styles and structures, gate level simulations, functional level simulations, debugging HDL, implementing and fitting into hardware, closing timing, routing and working with backend vendors. I am a good communicator and have good ethics. I always strive to deliver quality work on time and within budget. Please send me a message if you have questions or need specifics.

The job position posted on the company’s webpage is a good fit for me, given my experience in the field of FPGAs, and Embedded Systems. I am confident that I fulfill all the requirements that the company is looking for in an Engineer, especially for my skills in Verilog, HLS, Networking Protocols, Linux, Python, C/C++, and Firmware design. Additionally, I can be an excellent asset at finding bugs and solving them right the way given my experience in programming FPGAs, and ARM-based SOC processors. Moreover, I consider myself very confident in coding algorithms while optimizing and distributing all computer resources wisely, all thanks to my comprehension of the computer architecture of any system. In addition to that, I have extensive experience designing and testing communication interfaces such as SPI, I2C, VGA, HDMI, LVDS, PCI-E, and I have also worked with DMAs for high-speed acquisition purposes.

1.0 year of experience in Analog layout design 3.0 years of experience in FPGA and Embedded System Familiar with device driver development with many interfaces (I2C, UART, SPI, AXI protocol), extensive knowledge about FIFO, Xilinx IP, SDRAM, DDR3, DDR4, Ethernet protocol Experienced in system integration, timing constraints resolution & timing analysis Familiar with Verilog HDL, VHDL, SystemVerilog, C, TCL, Perl Experienced in using EDA tools including: Modelsim, Quartus, Xilinx Vivado, ISE, XPS, SDK, LEDA, VCS, Design Compiler, Prime Time, IC Compiler experienced in Aurora 8b10b, 7-series, ultrascale GTX/GTH Transceiver