Implementation of keccak256 algorithm

The task is to develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with [login to view URL]; a. The source can be taken as [login to view URL] MVis-tokenminer 2.1.17; 2. The basis of the hash function is to take the source code [login to view URL]; a. The keccak256 algorithm should operate at the maximum FPGA frequency xcku035-1ffva1156c; b. The algorithm must use a minimum of LUT; c. The algorithm must use DSP Slices and Block RAM; d. The number of streams (copies of the algorithm) should be limited only by the available FPGA resources xcku035-1ffva1156c; 3. The algorithm should be implemented verification of the results of the calculation of the hash function; 4. FPGA must transmit information over the Ethernet interface (UDP protocol); 5. Basic information for transmitting the value of Nonce corresponding to the goal (current complexity); 6. Supporting information is shown in the application Interfaces.pdf. 7. Ethernet interaction scheme with xcku035-1ffva1156c chip. See the application [login to view URL] Materials presented at the end of the project: 1. The initial data of the implemented keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c (Xilinx Vivado Design Suite) 2. Data on the maximum hash rate keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c given the maximum number of threads (copies of the algorithm) 3. Provide materials confirming the operation of keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c Additional materials will be sent in a personal message to the appropriate candidate for this job.