2 system Bus arbiter in Verilog using synchronizer for clock domai crossing

Hello! Please check my profile and reviews to know about me and my work. It would be great if I could hhelp you out. Thank you!

Hi I am a researcher and circuit designer in VLSI. I have the experience in designing of arbiter for network on chip in verilog and schematic design. You can check my profile for project completion rate and reviews from client. Give the specification on chat . Thank you

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I am a graduated electronics engineer from faculty of engineering Cairo university with very good with honor grade,4 years experience in Verilog, I have done a lot of projects using Verilog &VHDL also my graduation project was the implementation of 5G receiver using Verilog My Verilog projects: state machines, clock divider, clock gating, ALU , 16-bit mips , UART , CRC , interleaver , Demapper, Register file ...

MASTERS IN ELECTRICAL ENGINEERING GOOD IN VERILOG/VHDL HELLO DEAR CLIENT I have gone through your project details and the work is DOABLE since its within my area of EXPERTISE.I will tackle are required guideline to deliver desired goal Please consider my bid. THANKS