Hello
I had already have this Verilog code and TB with me.
I have been working with Verilog for over five years, and during that time, I have gained a deep understanding of the language and its application in the design and verification of digital circuits. I have experience in developing Verilog modules for FPGA and ASIC designs, and I have also worked with various verification tools, such as ModelSim, QuestaSim, and Synopsys VCS.
Skill-
Security Verification Tools: Cadence JasperGold, SPV, Cadence IFV.
Front-End Design:
1. RTL Design And Synthesis: Synopsys Design Compiler, Cadence Genus
2. Functional Verification: Synopsys VCS, NCSim.
3. Logic Equivalence Check: Synopsys Formality, Cadence Conformal LEC
Hardware Description Languages: Verilog, System-Verilog, System-Verilog Assertion,Coverage, UVM.
Scripting Languages: Tcl-tk, Perl, Linux.
Programming Languages: C, Python.
FPGA Design: Vivado,Intel Quartus Prime Lite (version 18.00).
In addition to my technical skills, I am an effective communicator and team player, capable of working collaboratively with cross-functional teams to ensure successful project delivery. My strong problem-solving and analytical skills have been an asset to my previous employers, where I have been able to identify and resolve complex technical issues.
You come here right place to talk for your project.
I am ready to solve your project
waiting a positive response from your side