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Avatari i Përdoruesit
$35 USD / orë
Flamuri i EGYPT
beni suef, egypt
$35 USD / orë
Aktualisht është 12:59 m.d. këtu
U bashkua maj 11, 2020
0 Rekomandime

Moaz Khaled Feriz K.

@moaazkh96

verified.svg
 5,0 (73 përshtypje)
5,8
5,8
93%
93%
$35 USD / orë
Flamuri i EGYPT
beni suef, egypt
$35 USD / orë
99%
Punët e Plotësuara
83%
Brenda Buxhetit
95%
Në Kohë
21%
Shpeshtësia e Rimarrjes në Punë

Digital Design Engineer. (FPGA, ASIC)

I am a full-time digital design engineer, I have a broad knowledge of digital design in ASIC and FPGA using both VHDL and Verilog. Interested in VLSI careers in both front-end (RTL) and back-end (syn, pnr....). I started my career on freelancing platforms 2.5 years ago, - Helping researchers and industry people to develop their digital designs, implement their papers. - Solving code problems. - Optimizing designs for speed, area and power. Through these projects I have improved my technical skills, applied my knowledge and grown my network with people around the globe. I have customers in USA, EU, China, India, Pakistan ... and many other countries, all of them were happy with their work done and so would you :) I am using the following tools and languages; FPGA : Vivado, ISE, and Quartus. ASIC : VCS, DVE, DC and spyglass. HDL : Verilog, System Verilog, VHDL. Scripting : Perl, tcsh, csh, tcl.
Freelancer Verilog / VHDL Designers Egypt
Shikoni të gjitha Verilog / VHDL Designers në Egypt

Kontaktoni Moaz Khaled Feriz K. për punën tuaj

Identifikohu për të diskutuar çdo detaj gjatë bisedës.

Portfolio

6639217
I have designed a multiplier using only one adder in logsim program with a full report for submission.
design FSM multiplier
I have designed a multiplier using only one adder in logsim program with a full report for submission.
design FSM multiplier
I have designed a multiplier using only one adder in logsim program with a full report for submission.
design FSM multiplier
I have designed a multiplier using only one adder in logsim program with a full report for submission.
design FSM multiplier
6605692
designing and simulating both CMOs and NMOS inverters using Hspice providing a professional report for submission
CMOS design by Hspice
designing and simulating both CMOs and NMOS inverters using Hspice providing a professional report for submission
CMOS design by Hspice
designing and simulating both CMOs and NMOS inverters using Hspice providing a professional report for submission
CMOS design by Hspice
6584148
Verilog code design
a digital class assignment to make a verilog code of subtractor in behavioural modelling and test bench. I deliver it in few hours with full report ready to upload.
Verilog code design
a digital class assignment to make a verilog code of subtractor in behavioural modelling and test bench. I deliver it in few hours with full report ready to upload.
Verilog code design
6576510
a project of generation a Gray code on model sim by system Virloge then deploy it on FPGA.
Gray code display
6516140
A CS course project.
car number plate detection
6515736
1 Kbit SRAM layout using cadence, with clear DEC, LVS, PEX checks.
Cadence layout
6639217
I have designed a multiplier using only one adder in logsim program with a full report for submission.
design FSM multiplier
I have designed a multiplier using only one adder in logsim program with a full report for submission.
design FSM multiplier
I have designed a multiplier using only one adder in logsim program with a full report for submission.
design FSM multiplier
I have designed a multiplier using only one adder in logsim program with a full report for submission.
design FSM multiplier
6605692
designing and simulating both CMOs and NMOS inverters using Hspice providing a professional report for submission
CMOS design by Hspice
designing and simulating both CMOs and NMOS inverters using Hspice providing a professional report for submission
CMOS design by Hspice
designing and simulating both CMOs and NMOS inverters using Hspice providing a professional report for submission
CMOS design by Hspice
6584148
Verilog code design
a digital class assignment to make a verilog code of subtractor in behavioural modelling and test bench. I deliver it in few hours with full report ready to upload.
Verilog code design
a digital class assignment to make a verilog code of subtractor in behavioural modelling and test bench. I deliver it in few hours with full report ready to upload.
Verilog code design
6576510
a project of generation a Gray code on model sim by system Virloge then deploy it on FPGA.
Gray code display
6516140
A CS course project.
car number plate detection
6515736
1 Kbit SRAM layout using cadence, with clear DEC, LVS, PEX checks.
Cadence layout

Vlerësimet

Ndryshimet u ruajtën
Duke shfaqur 1 - 5 nga 50+ përshtypje
Filtroni vlerësimet sipas:
5,0
$2 000,00 USD
fpga video processing pipeline. -- 2
Good and professional delivery. Excellent communication
Electronics
Verilog / VHDL
FPGA
Avatari i Përdoruesit
Flamuri i Felix L.
@felixlaz
•
10 months ago
5,0
₹5 000,00 INR
Verilog implementation of adam method
Moaz Khaled Feriz K is very dedicated towards work and shown results on time. I am happy and very much satisfied with his work.
Verilog / VHDL
FPGA
ASIC
Altera Quartus
+1 më shumë
J
Flamuri i Jillela M.
@jillelamahesh111
•
11 months ago
5,0
₹4 500,00 INR
Implementation of Gradient Descent Optimization Algorithms on FPGA in Verilog language which is synthesizable.
I love working with Moaz Khaled Feriz and he is very dedicated towards the project, he is the best freelancer which I have seen so far
Verilog / VHDL
FPGA
ASIC
Altera Quartus
+1 më shumë
J
Flamuri i Jillela M.
@jillelamahesh111
•
1 year ago
4,8
$473,01 USD
Debugging VHDL code for Nios Processor
He Know the subject very well [29 December, 2022] Knows subject very well [29 December, 2022] Knows subject very well [29 December, 2022] Knows subject very well [29 December, 2022] Knows subject very well
Verilog / VHDL
FPGA
ASIC
Altera Quartus
+1 më shumë
W
Flamuri i Kondi Wilfried K.
@Wkou23
•
1 year ago
5,0
$250,63 USD
MIPS Processor
He was awesome to work with. [26 December, 2022] Awesome work
Verilog / VHDL
FPGA
ASIC
Altera Quartus
+1 më shumë
M
Flamuri i Murjan U.
@murjanrahman
•
1 year ago

Përvoja

digital design engineer

freelancer .com
maj 2020 - E tashme
I am helping researchers and post-grade students to implements their design as RTL with VHDL, Verilog and SystemVerilog for both FPGA and ASIC. I am using Vivado, ISE, Quartus and Modelsim. also I have experience in ASIC EDA tools like DC, ICC, ICC2 and PrimeTime.

Arsimi

Bachlore degree in nano-electronincs

Zewail City of Science and Technology, Egypt 2016 - 2021
(5 years)

Kontaktoni Moaz Khaled Feriz K. për punën tuaj

Identifikohu për të diskutuar çdo detaj gjatë bisedës.

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preferredfreelancer-1.png Preferred Freelancer Program SLA 1 87%
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Aftësitë më të mira

Verilog / VHDL 67
FPGA 55
ASIC 22
Altera Quartus 22
Digital ASIC Coding 21

Kërko punonjës të pavarur të ngjashëm

Verilog / VHDL Designers in Egypt
Verilog / VHDL Designers
Field-Programmable Gate Array Experts
ASIC Engineers

Shfleto ekspozita të ngjashme

Verilog / VHDL
FPGA
ASIC
Altera Quartus
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