Improve performance of the power and delay by apply any three methodlogy for Ring VCO tanner tool based design

I am attaching a paper . you have to improve the results of area and delay by use any methodology . you can use one methodology for reduce the delay and area (like by reduce the number of transistor or any other methodology in which you will be comfortable ) and second methodology for improve the power consumption from the attached paper power results(you can improve the power results by apply GDI and dual VDD technique ). So like this you have to improve the results of power ,area and delay . we have to use tanner tool and file 130nm or below 130 nm . if you don't have file of 130 nm then i can give you the 130 nm file but you have file less then 130 nm then you have to use that .