Hello,
I am a FPGA engineer with good experience in Verilog programming.
I already have done this type of image processing work on FPGAs.
here is some of the top level code.
EdgeDetect uEdgeDetect
(
.iClk(psync_cap),
.iRstn(rst_nn),//
.iDataValidIn(DataValid_HotTrack),
.iDataIn(DataOut_HotTrack),
.iDataStart(DataStart_HotTrack),
.iFuncEn(EdgeDetect_En),
.iHighlightEn(HighlightEn),
.iThreshhold(Para[12:0]),//13'd400
.oDataValid(DataValid_ED),
.oDataStart(DataStart_ED),
.oDataOut(DataOut_ED),
.oMatrixX(MatrixX),
.oMatrixY(MatrixY),
.oMatrix(Matrix)
);
NonMaxSuppression uNMS
(
.iClk(psync_cap),
.iRstn(rst_nn),
.iDataValidIn(DataValid_ED),
.iDataIn(DataOut_ED),
.iMatrix(Matrix),
.iMatrixX(MatrixX),
.iMatrixY(MatrixY),
.iDataStart(DataStart_ED),
.iFuncEn(EdgeDetect_En),//
.iThresh(Para[27:24]),
.oDataValid(DataValid_NMS),
.oDataStart(DataStart_NMS),
.oDataOut(DataOut_NMS)
);
EdgeCompletion uEdgeCompletion
(
.iClk(psync_cap),
.iRstn(rst_nn),
.iDataValidIn(DataValid_NMS),
.iDataIn(DataOut_NMS),
.iDataStart(DataStart_NMS),
.iFuncEn(EdgeDetect_En),
.iThresh(Para[23:20]),
.oDataValid(DataValid_EC),
.oDataStart(DataStart_EC),
.oDataOut(DataOut_EC)
);
Looking forward to hearing back from you.