VLSI PROJECT -- 3

Hi there,I'm biddin on your project "VLSI PROJECT -- 3"Verilog / VHDL, Electronics, Engineering, Circuit Design and Electrical Engineering Comparison of CMOS, pseudo NMOS and transmission gate logic in terms of power-delay-area I have read your project description and i'm a Professional Engineer therefore i can do this project for you perfectly.I still have a few questions. please leave a message on my chat so we can discuss the budget and deadline of the project. Thanks. .. .

I am a third-year student from the Department of Electronics and Electrical Communication Engineering at the Indian Institute of Technology, Kharagpur. In my course of VLSI Engineering, I have completely familiarized with these methods of circuit design (Static CMOS, Dynamic CMOS, pseudo NMOS, pass transistor logic and transmission gate logic and their power-delay-area requirements). But I don't know its coding part by using cadence virtuoso using AMI 0.6um or TMSC 0.4um. Though I know the theory, I have very good grip on circuit design using verilog hardware language. Though I have just started doing freelancing, I shall be committed to my work. This is the domain of my interest. I shall readily acquaint myself with any pre-requisites needed for the project. I hope to be able to go beyond the problem statement and produce the quality of the research work required for the project. I request you to please consider. Thank you.

Hello, I saw your posting. I am an electronic expert. I have good experience with VHDL, circuit design. Please contact me. Please send me a chat. thanks.