Verilog RTL reader-translator-writer

Here's the description of the project we need. 1) Verilog RTL reader, that reads an RTL module (flat or hierarchical) and builds a some kind of internal representation tree (maybe VPI or something else). 2) Translator, that creates another verilog RTL module with accordance to specification we provide. We anticipate this will be the biggest part of the project. Besides, somone may already have a verilog reader/writer, then this will be the only part of project you will have to create. The translator will be static, there will be no need to compile or simulate verilog RTL. In fact it's very simple, there's just going to be a rule how to translate every verilog statemen (assignment statements, loops, etc...). 3) Verilog writer, to dump the translated RTL. We would like it to be written in C++, in a nice OO way. It would be better if it didn't require any external libs, so it could compile both in Linux (gcc) and Win (VC 6). ## Deliverables 1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables): a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment. b) For all others including desktop software or software the buyer intends to distribute: A software installation package that will install the software in ready-to-run condition on the platform(s) specified in this bid request. 3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement). ## Platform Windows Visual Studio 6 Linux GCC