ASIC Synthesis

My research objective is to design an asynchronous barrel shifter in order to reduce its processing time compared to its synchronous counterpart that works on the worst-case delay model. I will design both synchronous and asynchronous shifter circuits in the same ASIC technology to compare their performance. The research aim is to reduce the worst-case delay of the shifter circuit to an average case delay by introducing an asynchronous design technique. I am also looking for a possibility to calculate the circuit delay using FPGA. I am currently using Vivado for functional verification of my code, but it is optimizing the circuit and I am not sure whether it will be able to calculate the delay of the actual circuit without optimizing. I have designed a 32-bit barrel shifter that requires 5 stages, but Vivado is implementing it using 3 stages only. I have also utilized "KEEP=on" to avoid the optimization, but it is not working and still using only 3 stages.