VHDL / Verilog coding for Altera Native PHY

Looking for person with background in VHDL or Verilog and experience with Altera Quartu software and Altera IPs. This job is about debugging/configuring Native PHY for use with SATA protocol. We have most of the design, but some low-level Altera IP configuration is not working correctly. Can provide FPGA board we are using for debugging (within US) if needed. This should be a very quick project for someone familiar with Altera Native PHY and IPs.